Chapter 3/ Hardware Briefing

� Address line 1 (1 bit)

� Address line 2 (1 bit)

� Address line 3 (I bit)

32-bit

� address

� Address line 30 (1 bit)

� Address line 31(1 bit)

� Address line 32 (1 bit)�

->■ Data bus (32-bit chunk of data)

Control bus (read/write signal)

Figure 3.1

known as the bottom of meinory, or low memory. The region of memory near

the final byte is known as high memory.

Address lines are a set of wires connecting the processor to its RAM chips.

Each address line specifies a single bit in the address of a given byte. For

example, IA-32 processors, by default, use 32 address lines (see Figure 3.1).

This means that each byte is assigned a 32-bit address such that its address

space consists of 2�� addressable bytes (4 GB). In the early 1980s, the Intel

8088 processor had 20 address lines, so it was capable of addressing only 2�®

bytes, or 1 MB.

It's important to note that the actual amount of physical memory avail¬

able doesn't always equal the size of the address space. In other words, just

because a processor has 36 address lines available doesn't mean that the

computer is sporting 64 GB worth of RAM chips. The physical address space

defines the maximum amount of physical memory that a processor is capable

of accessing.

With the current batch of IA-32 processors, there is a feature that enables

more than 32 address lines to be accessed, using what is known as physical

address extension (PAE). This allows the processor's physical address space

to exceed the old 4-GB limit by enabling up to 52 address lines.

Note: The exact address width of a processor is specified by the MAXPHYADDBvahe

returned by CPUID function 80000008H. In the Intel documentation for IA-32 proces¬

sors, this is often simply referred to as the "M" value. We'll see this later on when we

examine the mechanics of PAE paging.

To access and update physical memory, the processor uses a control bus and a

data bus. A bus is just a series of wires that connccts the processor to a hard-