Chapter 3/ Hardware Briefing

IA-32 Memory Models

To gain a better understanding of how the IA-32 processor fatnily offers

memory protection services, we'll start by examining the different ways in

which memory can be logically organized by the processor. We'll examine

two different schemes:

■ The flat memory model.

■ The segmented memory model.

Flat Memory Model

Unlike the physical model, the linear model of memory is somewhat of an

abstraction. Under the flat model, memory appears as a contiguous sequence

of bytes that are addressed starting from 0 and ending at some arbitrary

value, which I'll label as N (see Figure 3.2). In the case of IA-32, N is typi¬

cally — 1. The address of a particular byte is known as a linear address.

This entire range of possible bytes is known as a linear address space.

At first glance, this may seem very similar to physical memory. Why are we

using a model that's the identical twin of physical memory?

In some cases, the flat model actually ends up being physical memory . . . but

not always. So be careful to keep this distinction in mind. For instance, when

a full-blown memory protection scheme is in place, linear addresses are used

smack dab in the middle of the whole address translation process, where they

bear no resemblance at all to physical memory.

Linear Address = N-3

Byte at Address

N

Byte at Address

N-l

Byte at Address

N-2

Byte at Address

N-3

1

Byte at Address

3

Byte at Address

2

Byte at Address

1

Byte at Address

0

> Linear Address Space

Figure 3,2