3.4 Protected Mode

these same tactics again several times later on in the book. Before we do so,

you'll need to understand how the current generation of processors manages

and protects memory. This is the venue of protected mode.

3.4 Protected Mode_

Like real mode, protected mode is an instance of the segmented memory

model. The difference is that the process of physical address resolution is

not performed solely by the processor. The operating system (whether it's

Windows, Linux, or whatever) must collaborate with the processor by main¬

taining a whole slew of special tables that will help the processor do its job.

Although this extra bookkeeping puts an additional burden on the operating

system, it's these special tables that facilitate all of the bells and whistles

(e.g., memory protection, demand paging) that make IA-32 processors fea¬

sible for enterprise computing.

The Protected-Mode Execution Environment

The protected-mode execution environment can be seen as an extension of

the real-mode execudon environment. This resemblance is not accidental;

rather, it reflects Intel's desire to maintain backwards compatibility. As in real

mode, there are six segment registers, four general registers, three pointer

registers, two indexing registers, and a flags register. The difference is that

most of these registers (with the excepdon of the 16-bit segment registers) are

now all 32 bits in size (see Figure 3.9).

There's also a number of additional, dedicated-purpose registers that are used

to help manage the execution environment. This includes the five control

registers (CRO through CR4), the global descriptor table register (GDTR), the lo¬

cal descriptor table register (LDTR), and the interrupt descriptor table register

(IDTR). These eight registers are entirely new and have no analogue in real

mode. We'll touch on these new registers when we get into protected mode

segmentation and paging.

As in real mode, the segment registers (CS, DS, SS, ES, FS, and GS) store seg¬

ment selectors, the first half of a logical address (see Table 3.7). The differ¬

ence is that the contents of these segment selectors do not correspond to a

64-KB segment in physical memory. Instead, they store a binary structure

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