Chapter 3/ Hardware Briefing

this case is an offset value used to help generate a linear address. In addition,

although ESP, EBP, ESI, and EBP are 32 bits in size, you can still reference their

lower 16 bits using the older real-mode identifiers (SP, BP, SI, and Dl).

Of the 32 bits that make up the EFLAGS register, there are just two bits that

we're really interested in: the trap flag (TF; bit 8 where the first bit is desig¬

nated as bit 0) and the interrupt enable flag (IF; bit 9). Given that EFLAGS is

just an extension of FLAGS, these two bits have the same meaning in protected

mode as they do in real mode.

Protected-Mode Segmentation

There are two facilities that an IA-32 processor in protected mode can use to

implement memory protection:

■ Segmentation.

■ Paging.

Paging is an optional feature. Segmentation, however, is not. Segmentation

is mandatory in protected mode. Furthermore, paging builds upon segmenta-

don, and so it makes sense that we should discuss segmentation first before

diving into the details of paging.

Given that protected mode is an instance of the segmented memory model,

as usual we start with a logical address and its two components (the segment

selector and the effective address, see Figure 3,10),

In this case, however, the segment selector is 16 bits in size, and the effec¬

tive address is a 32-bit value. The segment selector references an entry in a

table that describes a segment in linear address space. So instead of storing

the physical address of a segment in physical memory, the segment selec¬

tor indexes a binary structure that contains details about a segment in linear

address space. The table is known as a descriptor table and its entries are

known, aptly, as segment descriptors.

A segment descriptor stores metadata about a segment in linear address space

(access rights, size, 32-bit base linear address, etc,). The 32-bit base linear

address of the segment, extracted from the descriptor by the processor, is then

added to the offset provided by the effective address to yield a linear address.

Because the base linear address and offset addresses are both 32-bit values, it

makes sense that the size of a linear address space in protected mode is 4 GB

(addresses range from 0x00000000 to OxFFFFFFFF).

90 I Part I