Chapter 3/ Hardware Briefing

Protected-Mode Paging

Recall 1 mentioned that paging was optional. If paging is not used by the resi¬

dent operating system, then life is very simple: The linear address space being

referenced corresponds directly to physical memory. This implies that we're lim¬

ited to 4 GB of physical memory because cach linear address is 32 bits in size.

If paging is being used, then the linear address is nowhere near as intuidve.

In fact, the linear address produced via segmentation is actually the starting

point for a second phase of address translation. As in the previous discussion

of segmentation, I will provide you with an overview of the address transla¬

tion process and then wade into the details.

When paging is enabled, the linear address space is divided into fixed

size-plots of storage called pages (which can be 4 KB, 2 MB, or 4 MB in

size). These pages can be mapped to physical memory or stored on disk. If

a program references a byte in a page of memory that's currently stored on

disk, the processor will generate a page fault exception (denoted in the Intel

documentation as #PF) that signals to the operating system that it should

load the page to physical memory. The slot in physical memory that the page

will be loaded into is called a page frame. Storing pages on disk is the basis

for using disk space artificially to expand a program's address space (i.e.,

demand paged virtual memory).

Note: For the purposes of this book, we'll stick to the case where pages are 4 KB in size

and skip the minutiae associated with demand paging.

Let's begin where we left off: In the absence of paging, a linear address is a

physical address. With paging enabled, this is no longer the case. A linear ad¬

dress is now just another accounting structure that's split into three subfields

(see Figure 3.13).

32-bit Linear Address (under paging)

Bit 31 22 21 12 11 Bit 0

O-bit index into page directory 10-bit index into page table 12-bit offset into a physical page

Figure 3.13

In Figure 3.12, only the lowest order field (bits 0 through 11) represents a

byte offset into physical memory. The other two fields are merely array indi¬

ces that indicate relative position, not a byte offset into memory.