3.4 Protected Mode

The third field (bits 22 through 31) specifies an entry in an array structure

known as the page directory. The entry is known as a page directory entry

(PDE). The physical address (Ht�f the linear address) of the first byte of the

page directory is stored in control register CR3. Because of this, the CR3 regis¬

ter is also known as the page directory base register (PDBR).

Because the index field is 10 bits in size, a page directory can store at most

1,024 PDEs. Each PDE contains the base physical address {not the, linear ad¬

dress) of a secondary array structure known as the page table. In other words,

it stores the physical address of the first byte of the page table.

The second field (bits 12 through 21) specifies a particular entry in the page

table. The entries in the page table, arranged sequentially as an array, are

known as page table entries (PTEs). Because the value we use to specify

an index into the page table is 10 bits in size, a page table can store at most

1,024 PTEs.

By looking at Figure 3.14, you may have guessed that each PTE stores the

physical address of the first byte of a page of memory (note this is a physi¬

cal address, not a linear address). Your guess would be correct. The first field

Physical

Address Spate

Physical

Address

Figure 3.14

Parti I 95