3.4 Protected Mode

that settings made at the PDE level can cascade down to all of the pages

maintained by page tables underneath it.

Looking at Figure 3.17, you can see that there's a lot going on. Fortunately,

from the standpoint of memory protection, only two fields (common to both

the PDE and PTE) are truly salient:

■ The U/S nag.

■ The W flag.

The U/S flag defines two disdnct page-based privilege levels: user and super¬

visor. If this flag is clear, then the page pointed to by the PTE (or the pages

underneath a given PDE) arc assigned supervisor privileges. The W flag is

used to indicate if a page, or a group of pages (if we're looking at a PDE), is

read-only or writable. If the W flag is set, the page (or group of pages) can be

written to as well as read.

If you look at the blueprints in Figure 3,17, you may be wondering how a 20-bit base address

field can specify an address in physical memory (after all, physical memory in our case is

defined by at least 32 address lines). As in real mode, we solve this problem by assuming

implicit zeroes such that a 20-bit base address like 0x12345 is actually 0x12345[0][0][0] (or,

0x12345000).

This address value, without its Implied zeroes, is sometimes referred to as a page frame

number{P\�H). Recall that a page frame is a region in physical memory where a page worth

of memory is deposited. A page frame Is a specific location, and a page Is more of a unit

of measure. Hence, a page frame number Is just the address of the page frame (minus the

trailing zeroes).

In the case of paging with PAE (see Figure 3.18), the PDPTE, PDE, and PTE

structures that we deal with are essentially twice as large; 64 bits as opposed

to 32 bits. The flags are almost identical. The crucial difference is that the base

physical addresses are variable in size, depending upon the number of address

lines that the current processor has available (i.e., HAXPHYADDR, a.k.a. M). As

expected, the two fields we're interested in are the U/S flag and the W flag.

Part I I 99