3.4 Protected Mode

CR4

Bit 31 18 17 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved (i.e., zero)

OSX

PCI

SMX

VMX

OSX

OSF

PCE

PGE

MCE

PAE

PSE

DE

TSD

PVI

VME

CR3

Bit 31

Page Directory Base Address

12 11

5 4

PCD PWT

CR2

Bit31

Linear Address that has caused a page fault

CRl

Bit31

Reserved (i.e., not used, by Intel)

CRO

31 30 29

18

16

PG

CD

NW

AM

WP

NE

ET

TS

EM

MP

PE

Flags of Particular Intere.st

Page Directory Base Address in CR3

WP (Write Protect Bit) in CRO—When set, prevents writing into read-only user-level pages

Other Flags of Note

CRO; PG flag—enables paging when set

CRO; PE flag—enables protcctcd mode when set

(set by OS when il makes the jump I'rom real mode)

CR4; PSE flag—enables larger page sizes when set (e.g., 2 or 4 MB)

CR4: PAE flag—when set it allows a 36-bit physical address space to be used

Figure 3.19

The remaining control registers are of passing interest. I've included tliem in

Figure 3.19 merely to help you see where CRO and CR3 fit in. CRl is reserved,

CRZ is used to handle page faults, and CR4 contains flags used to enable PAE

and larger page sizes,

In the case of paging under PAE, the format of the CR3 register changes

slightly (see Figure 3.20). Specifically, it stores a 27-bit value that represents

a 52-bit physical address. As usual, this value is padded with implied zero

bits to allow a 27-bit address to serve as a 52-bit address.

Parti I 101