3.5 Implementing Memory Protection

Table 3,12 Segmentation Facilities

Segmentation Construct

Memory Protection Components

Segment selector

RPL field

CS and SS registers

CPL field

Segment descriptors

Segment limit, S flag, type field, DPL field

Gate descriptor

DPL field

GDT

Segment and gate descriptors

IDT

Gate descriptors

GDTR

GDT size limit and base address (GDTR instruction}

IDTR

IDT size limit and base address (LIDT instruction)

#GP exception

Generated by CPU when segment check is violated

CRO register

RE flag, enables segmentation

Paging offers the same sort of facilities, but on a finer level of granularity

with fewer options (see Table 3.13). Using segmentation is mandatory, even

if it means setting up a minimal scheme so that paging can be used. Paging,

in contrast, is entirely optional.

Table 3,13 Paging Facilities

Paging Construct

Memory Protection Components

PDPT

Base physical address of a page directory

PDE

U/S flag and the R/W flag

Page directory

Array of PDEs

PTE

U/S flag and the RAV flag

Page table

Array of PTEs

CR3

Base physical address of a PDPT or page directory

CRO

WP flag, PG flag enables paging

In the end, it all comes down to a handful of index tables that the operating

system creates and populates with special data structures (see Figure 3.27).

These data structures define both the layout of memory and the rules that

the processor checks against when performing a memory access. If a rule is

violated, the processor throws an exception and invokes a routine defined by

the operating system to handle the event.

Parti I 113