085

844 E. Charleston Road, Palo Alto, CA

37° 25′ 19.02″ N, 122° 6′ 12.18″ W

Fairchild and the Fairchildren

Shockley Semiconductor (see Chapter 84) spawned the prototypical Silicon Valley startup company, Fairchild Semiconductor, founded in 1957. Innovative yet focused on products, not just research, Fairchild went on to spawn many other Silicon Valley greats (including Intel, LSI Logic, and AMD), and its offspring are frequently referred to as the Fairchildren. And it was at Fairchild that the planar process for silicon chip manufacturing was invented.

Around the same time, in 1958/1959, Jack Kilby (at Texas Instruments) and Robert Noyce (at Fairchild) invented the integrated circuit, where multiple transistors (and other components) were made on a single piece of silicon. Kilby built a circuit based on the mesa process (see sidebar) and connected the components with fine gold wires; Noyce’s circuit used the planar process, which had superior wiring. The planar process won the day, but Kilby won the Nobel Prize.

Using the planar process, Fairchild was able to build working integrated circuits and started supplying prototypes in 1960. In 1961 it announced a line of integrated circuits with the claim that they would reduce the size of a computer by up to 70%. The simple circuits included logic and flip flops (which can act as a single bit of memory, being either on or off), and were the forerunners of the microchip revolution that continues to this day. Each chip had just a few transistors on it—a flip flop can be made with just two—but the number of transistors on a chip would rapidly increase.

In 1965 Gordon Moore (one of Fairchild’s founders) wrote an article in Electronics entitled “Cramming More Components onto Integrated Circuits.” In it he noted that the number of components on an integrated circuit would double every two years (he estimated that by 1975 there would be around 65,000 components on a single chip). This prediction is now known as Moore’s Law and still holds true today (for example, the Intel Itanium Tukwila processor has 2 billion transistors on a single chip). The law has also been extended into other areas of digital electronics, including hard disk capacity and the number of pixels per dollar on digital cameras.

Fairchild grew and was successful in the new integrated circuit marketplace (playing second fiddle to Texas Instruments), but in 1968 Gordon Moore and Robert Noyce left after the company got into financial trouble. Their next startup, Intel, is a household name. Fairchild Semiconductor exists to this day.

The actual Fairchild building is still standing at 844 E. Charleston Road in Palo Alto. Unfortunately, like the Shockley Semiconductor Laboratory building, there’s no actual technology to be seen (the building is not even occupied by a technology firm), but a photograph of the scientific tourist next to the state historic monument marker is a must for any nerd’s photo album.

After you’ve had your photo taken at the Fairchild building, check out the HP Garage (see Chapter 90), which is just a short drive away, also in Palo Alto.

Practical Information

The Fairchild building is now occupied by a design firm called Collective Creations. Outside the building is a plaque erected by the California Department of Parks and Recreation, commemorating it as the site of the first “commercially practicable integrated circuit.”

The Planar Process

Making integrated circuits (or silicon chips, as they are commonly called) requires building layers of semiconducting material (P- and N-type; see pages 114 and 324) to make transistors and other components. The components are then linked together with metal wiring, and external wires are connected so that the chip can be wired up to a circuit board.

Chips were initially created by the “mesa process.” A wafer of silicon was made with layers of N- and P-type silicon on it; then, powerful chemicals were used to etch valleys into the silicon, leaving flat-topped sandwiches of N- and P-type silicon in the right shape to form transistors. These sandwiches were named mesas, after the flat-topped hills found in some parts of the southwestern U.S.

At Fairchild, Jean Hoerni developed the more flexible planar process. The planar process starts with a wafer of silicon, which is covered with a layer of silicon oxide (SiO2) by oxidizing the silicon at high temperature in the presence of either steam or pure oxygen. The silicon oxide layer acts as an insulator.

Then, parts of the original silicon are exposed by etching through the silicon oxide. This is done by a photolithographic process in which a layer of a photoresist chemical is applied to the silicon oxide. This chemical is then exposed to ultraviolet light through a mask that defines the pattern of areas on the wafer that should be exposed. Where the light falls, the photoresist chemical changes. The wafer is then washed with a chemical that eats away the photoresist layer where it was exposed to ultraviolet light, and eats away the silicon oxide below, exposing the silicon wafer.

Silicon can be turned into a semiconductor by exposing it to chemicals that create impurities in the wafer. By exposing the silicon to boron, free electrons in the silicon are removed, and the exposed areas become a P-type semiconductor. If arsenic is used instead, an excess of free electrons is created in the silicon, and it becomes an N-type. This process is called doping.

Once doped, the silicon is covered over again with silicon oxide, and a new pattern can be etched into it using photolithography. In this way, different parts of the silicon can be doped to produce layers of N- or P-type semiconducting material in patterns that build up transistors and other components.

Finally, the components can be linked together by exposing just the areas where metal should connect with the wafer again using photolithography, spraying on a layer of aluminum, and etching away the aluminum to create wires. In modern integrated circuits, this process is applied repeatedly to build up layers of components and connections.

In Figure 85-1, an NPN transistor is created from a silicon wafer (which has been predoped so that it is N-type). This is done by first covering the wafer with silicon oxide (a), etching a hole in the oxide layer (b), doping to make a P-type area and reoxidizing (c), etching another hole (d), doping and reoxidizing an N-type area (e), etching holes for contacts (f), and finally applying aluminum to make contact points (g).

Figure 85-1. Building an NPN transistor by the planar process