2
Diode Circuits

2.1 The v‐i Characteristic of Diodes

Figure 2.1(a) shows the symbol for a diode, which allows an electric current (as a low resistance) in the forward direction, while blocking current (as a large resistance) in the reverse direction. Figure 2.1(b) shows the v‐i characteristic of a practical diode, which can be approximated by the Shockley diode equation (named after transistor coinventor William Bradford Shockley) or the diode law:

(2.1.1a,b) equation

Image described by caption and surrounding text. — **Figure 2.1** Symbol and *v‐i* characteristic of a diode.

where I_S, η, and V_T are the leakage (reverse saturation) current, the empirical constant (called the emission coefficient or ideality factor) between 1 and 2, and the thermal voltage, respectively.

Note that the thermal voltage V_T is given by

(2.1.2)

2.1.1 Large‐Signal Diode Model for Switching Operations

When the signal applied to such electronic devices as diodes and transistors is large in comparison with the bias level, they show ON‐OFF behavior, functioning like a switch.

The v‐i characteristic curve of a diode in terms of its static behavior can be approximated by a solid/dotted piecewise linear (PWL) line for the forward‐/reverse‐bias mode as depicted in Figure 2.2(a). According to the approximation, the operation of a diode in the forward‐/reverse‐bias mode is represented by the equivalent model depicted in Figure 2.2(b).

2.1.2 Small‐Signal Diode Model for Amplifying Operations

Figure 2.3(a) and (b) shows the high‐frequency AC models of forward‐/reverse‐biased diodes, respectively. Note that the junction (or depletion or transition) capacitance defined as the ratio of the incremental change (Δq_j) in the charge (in the depletion layer) to that (Δv_D) in the anode‐to‐cathode bias voltage v_D can be expressed as

PWL approximation of the v–i characteristic curve of a diode represented by solid and dashed curves (a) and PWL model of a diode consists of 2 resistors labeled rf and Rr, 2 ideal diodes, etc. (b). — **Figure 2.2** PWL approximation of the *v‐i* characteristic curve of a diode and the corresponding model.

Circuit diagrams of high-frequency AC model of a diode consists of a capacitor labeled Cj + Cd, resistor, etc. (a) and high-frequency AC model of a reverse-biased diode consists of a capacitor labeled Cj, etc. (b). — **Figure 2.3** High‐frequency AC (small‐signal) model of a diode.

(2.1.3)

where M: junction gradient coefficient, V_j: (built‐in) junction potential with the value of 0.5∼0.9 V for a Si (silicon) diode and 0.2∼0.6 V for a Ge (germanium) diode, and C_j0: zero‐bias junction capacitance

Note also that the diffusion (or transit time) capacitance due to the diffusion of carriers from anode to cathode in the forward‐bias mode can be expressed as

(2.1.4)

where t_T: transit or storage time taken for the charge to cross the diode, I_Q: diode current at the operating point Q, η: emission coefficient or ideality factor, and, images

Note also that the dynamic resistance r_d can be approximated as

(2.1.5)

2.2 Analysis/Simulation of Diode Circuits

The procedure of performing a large‐signal analysis for diode circuits can be summarized:

Assume (guess) the ON/OFF state of each diode.
For ON/OFF state, replace the diode by the forward‐/reverse‐bias model of each diode like the ones depicted in Figure 2.2(b).
Solve the circuit and verify the result and the assumptions:
- For a diode assumed to be ON (with v_D ≈ V_TD), the initial guess is justified if i_D > 0; otherwise, i.e. if i_D < 0, resume the analysis with the assumption that the diode is OFF.
- For a diode assumed to be OFF (with i_D = 0), the initial guess is justified if v_D < V_TD; otherwise, i.e. if v_D ≥ V_TD, resume the analysis with the assumption that the diode is ON.

2.2.1 Examples of Diode Circuits

See the following examples.

Example 2.1 Analysis of an AND Gate Using PWL Model

For the circuit of Figure 2.4(a), find the output voltage v_o to different values of input voltages {v₁, v₂} where the PWL diode model parameters in Figure 2.2(b) are r_f = 30 Ω, V_TD = 0.685 V, R_r = ∞ Ω, and I_s = 1 × 10^‐15 A. Note that all voltages are measured w.r.t. the reference node, which is grounded.

For v₁ = v₂ = 5 [V], we assume that D₁ and D₂ are OFF so that v_o = 5 V(High) as described by the equivalent in Figure 2.4(b1). We check the validity of this assumption:

Figure 2.4 A diode circuit functioning as an AND gate and its equivalents for different input values.

(E2.1.1)
For v₁ = 5 [V] and v₂ = 0 [V], we assume that D₁ is OFF and D₂ is ON as described by the equivalent in Figure 2.4(b2) so that we can get
(E2.1.2)

We check the validity of this assumption:

(E2.1.3)
For v₁ = v₂ = 0 [V], we assume that D₁ and D₂ are ON as described by the equivalent in Figure 2.4(b3) so that we can apply Kirchhoff's Voltage Law (KVL) to the inner/outer loops with to obtain
(E2.1.4)

We check the validity of this assumption:

(E2.1.5)

Are we lucky that all the assumptions have turned out to be true? Then let us try with another assumption for the last case. For v₁ = v₂ = 0 [V], we assume that D₁ is ON and D₂ is OFF as described by the equivalent in Figure 2.4(c) so that we can apply KVL to the inner loop to get

(E2.1.6)

We check the validity of this assumption:

(E2.1.7)

If we use the (nonlinear) exponential model (2.1.1) for a more exact analysis, the KVL equation in images can be set up as

(E2.1.8)

since the current through R = 4.7 kΩ is images . Here, Eq. (2.1.1b) has been used to express the diode voltage v_D in terms of the diode current i_D. To solve this nonlinear equation, the MATLAB function ‘fsolve()’ can be used as listed in the following script “elec02e01.m”:


%elec02e01.m
nVT=0.0259; Is=1e-15; % Thermal voltage, Reverse saturation current
rf=30; VTD=0.685; % Diode PWL model parameters
R = 4700;
vDi = @(iD)nVT*log(iD/Is+1); % Eq. (2.1.1b)
eq = @(i)vDi(i)+(2*R+270)*i-5; % Eq. (E2.1.8) with exponential model
%eq = @(i)VTD+(rf+2*R+270)*i-5; % KVL equation with PWL model
iD = fsolve(eq,1e-3) % Diode current
vD = vDi(iD) % Diode voltage
vo = 5 - R*2*iD % Output voltage

Running this script yields


 iD = 4.4522e-04,  vD = 0.6947,  vo = 0.8149

which is close to the above result (Eq. (E2.1.5)) of analysis using the PWL model.

Example 2.2 Analysis of a Two‐Diode Circuit Using CVD (Constant Voltage Drop) Model

For the circuit of Figure 2.5(a), replace the diodes (assumed to be ON) by the CVD model (that is, the PWL model with r_f = 0 Ω and V_TD = 0.7 V) and find the voltages v₁ and v₂. Compare them and those obtained using the exponential model (Eq. 2.1.1) with I_s = 10 × 10⁻¹⁵ A and ηV_T = 25.9 mV.

Note that there are four possible states for the two diodes D₁ and D₂: ON‐ON, ON‐OFF, OFF‐ON, and OFF‐OFF. First, assuming that both D₁ and D₂ are ON, we replace them by the Constant Voltage Drop (CVD) model to draw the equivalent as shown in Figure 2.5(b). Then the voltages v₁ and v₂ can easily be found as

(E2.2.1)

yielding

(E2.2.2)

Figure 2.5 A two‐diode circuit for Example 2.2.

However, images = −0.27 mA < 0 contradicts the assumption that D₁ is ON. That is why we make another assumption that D₁ and D₂ are ON and OFF, respectively, draw the corresponding equivalent as depicted in Figure 2.5(c) and get

(E2.2.3)

Still, images = 6.7 V > 0 contradicts the assumption that D₂ is OFF. That is why we make another assumption that D₁ and D₂ are OFF and ON, respectively, draw the corresponding equivalent as depicted in Figure 2.5(d) and get

(E2.2.4)

This yields images = v₁ = −0.2 V < 0 and images = i = 1.02 mA > 0, suiting the assumption that D₁ and D₂ are OFF and ON, respectively. Therefore, the solution is v₁ = −0.2 V and v₂ = v₁ − 0.7 = −0.9 V.

If we use the (nonlinear) exponential model (2.1.1) for a more exact analysis, KCL can be applied at nodes 1 and 2 to yield a set of two node equations in v₁ and v₂ as

(E2.2.5)

where Eq. (2.1.1a) has been used to express diode current i_D in terms of diode voltage v_D. To solve this set of nonlinear equations, the MATLAB function ‘fsolve()’ can be used as listed in the following script “elec02e02.m”:


%elec02e02.m
Is=10e-15; nVT=0.0259; % Diode exponential model parameters
Vs1=10; Vs2=-6; R1=1e4; R2=5e3; % Circuit parameter values
iD = @(vD)Is*(exp(vD/nVT)-1); % Eq. (2.2.1a)
eqs = @(v)[(Vs1-v(1))/R1-iD(v(1))-iD(v(1)-v(2));
           iD(v(1)-v(2))-(v(2)-Vs2)/R2]; % Eq. (E2.2.5)
v = fsolve(eqs,[1 1]), ID2=iD(v(1)-v(2))

Running this script yields the following, which is close to the above result with the CVD model:


 v = -0.2289  -0.8855,  ID2 = 0.0010

2.2.2 Clipper/Clamper Circuits

Figure 2.6(a1) and (a2) respectively show clipper circuits for clipping the upper and lower portion of the input signal above/below the reference level of (V₁ + V_D)/(−V₂ −V_D), which is determined by the DC voltage source connected in series with the diode. Figure 2.6(b1) and (b2) show their input and output voltage waveforms obtained from PSpice simulation. Running the following MATLAB script yields a similar result.


%elec02f06_1_clipper.m
Is=10e-15; nVT=0.0259; VD=0.7;
iD=@(vD)Is*(exp(vD/nVT)-1); % Eq. (2.2.1a)
t=[0:0.01:2.5]; vi=10*sin(2*pi*t); R=1e3; V1=5;
v10=0; Nt=length(t); options=optimoptions ('fsolve','Display','none');
for n=1:Nt
 eq = @(v)vi(n)-v-R*iD(v-V1); % KCL equation in v
 if n>1, v10=v(n-1); end; v(n)=fsolve(eq,v10,options);
end
plot(t,vi,'r:', t,v,'g', t,V1+VD,'k:')

Figure 2.6(a3) shows a two‐level clipper circuit, which combines two clipper circuits for clipping the upper and lower portions of the input signal so that the output voltage can be kept within the range of [−V₂ −V_D, V₁+V_D]. Figure 2.6(b3) shows its input and output voltage waveforms.

Figure 2.7(a1) and (a2) shows positive/negative clamper circuits (called clamped capacitors or DC restorers), which push the input signal (within [V_i,min, V_i,max]) upward/downward by the positive/negative capacitor voltage charged (when v_i = V_i,min/V_i,max), i.e. V_C = (−V_i,min + V_r −V_D)/(V_i,max −V_r −V_D) so that their outputs are related with their inputs as

(2.2.1a)

(2.2.1b)

Note that the trough/peak level of the positive/negative clamper outputs will be (V_r −V_D)/(V_r+V_D), respectively, where V_D depends on the capacitance C and how long C has been charged.

2.2.3 Half‐wave Rectifier

The diode in the circuit of Figure 2.8(a) can be represented by the CVD model as shown in Figure 2.8(b), which is valid in the forward mode of the diode, i.e. while v_i ≥ V_os where the offset or cut‐in voltage V_os (slightly less than the threshold voltage V_TD) is the diode voltage at which the diode starts to turn on. Here, we can find the cut‐in or ignition angle ϕ at which the diode starts to turn on:

(2.2.2)

Similarly, the extinction angle at the end of the (first) positive half‐cycle is π − ϕ (see Figure 2.8(c)). Note that the peak inverse voltage (PIV) of the diode is V_m.

2.2.4 Half‐wave Rectifier with Capacitor – Peak Rectifier

Figure 2.9.1(a) shows the PSpice schematic of a half‐wave rectifier composed of a diode, a capacitor, and a resistor, called a peak rectifier, which conducts in the forward direction for v_D ≥ V_TD = 0.65 V. Figure 2.9.1(b) and (c) shows the equivalent circuits of the rectifier for v_i ≥ v_o+V_TD and v_i < v_o+V_TD, respectively. Figure 2.9.1(d) shows the PSpice simulation result obtained from the Transient Analysis with Run_to_time of 40 ms. From this PSpice simulation result, we find the upper/lower limit V_H/V_L of the output voltage v_o(t) and the rising/falling period T_R/T_F as

Circuit diagrams illustrating a diode circuit (a) and the equivalent model with D ON (b) and the input/output voltage waveforms (c). — **Figure 2.8** A half‐wave rectifier and its input/output voltage waveforms.

To obtain these parameters, after getting the output voltage waveform in the PSpice A/D (Probe) window, click the Toggle Cursor button on the toolbar to activate the two cross‐type cursors on the graph. Then use the left/right mouse button and/or arrow/shift‐arrow key or click the appropriate toolbar button to move them to the peak/trough and read their coordinates from the Probe Cursor box. If you have two or more waveforms on the Probe window, you can choose one which you want to take a close look at by clicking the name of the corresponding variable under the graph.

To get the upper/lower limit V_H/V_L of the output voltage v_o(t) and the rising/falling period T_R/T_F via an analytical approach using MATLAB, we set up the following equations:

(2.2.3a)

(2.2.3b)

(2.2.3c)

Noting that V_H is already known as V_H = V_m − V_TD = 5 − 0.65 = 4.35, we solve this set of equations to find V_L = 3.23, T_R = 0.0018, and T_F = 0.0149 by saving these equations into an M‐file named, say, ‘halfwave_rectifier_eq.m’ and running the following MATLAB script “do_halfwave_rectifier.m.”


%do_halfwave_rectifier.m
clear
global Vm f VTD
Vm=5; f=60; VTD=0.65;
VH=Vm-VTD; % Local maximum (High Voltage) of vo(t)
R=1e4; C=5e-6;
x0=[0 0 0]; % Initial guess of [VL TR TF]
% VL: Low Voltage (Local Min) of vo(t), TR: Rise Time, TF: Falling Time
x=fsolve('halfwave_rectifier_eq',x0,optimoptions ('fsolve'),C,R)
VL=x(1); TR=x(2); TF=x(3);
fprintf('\n VH=%8.4f, VL=%8.4f, TR=%8.4f, TF=%8.4f\n', VH,VL,TR,TF)
function y=halfwave_rectifier_eq(x,C,R)
global Vm f VTD
VH=Vm-VTD; w=2*pi*f; T=1/f;
VL=x(1); TR=x(2); TF=x(3);
y=[VH*exp(-TF/R/C)-VL; % Eq. (2.2.3a)
   VH-VL-Vm*(1-cos(w*TR)); % Eq. (2.2.3b)
   TR+TF-T]; % Eq. (2.2.3c)

Now, to perform the MATLAB simulation of the rectifier circuit with capacitor filter in Figure 2.9.1(a), we discretize the integro‐differential equation for the voltage‐current relationship (VCR) of the capacitor as

(2.2.4a)

where

(2.2.4b)

The numerical solution process to find the output voltage of a half‐wave rectifier as shown in Figure 2.9.1(a) has been cast into the following MATLAB function ‘rectifier_RC()’. The following MATLAB script “elec02f09.m” uses this function to find v_o(t) of the half‐wave rectifier (in Figure 2.9.1(a)) as Figure 2.9.2 together with the values of V_H = 4.36, V_L = 3.26, T_R = 0.002, and T_F = 0.0147.


function [vo,vD,iD,iR]=rectifier_RC(vit,R,C,Is,nVT)
% vit = [vi; t]: 2-row matrix consisting of the input signal and time
% R,C = Resistance and Capacitance
% Copyleft: Won Y. Yang, wyyang53@hanmail.net, CAU for academic use only
if nargin<5, nVT=(273+27)/11605; end % Thermal voltage
iDv = @(vD)Is*(exp(vD/nVT)-1); % Eq. (2.1.1a)
[Nr,Nc]=size(vit);
if Nc==2, vi=vit(:,1); ts=vit(:,2); N=Nr;
 elseif Nr==2, vi=vit(1,:); ts=vit(2,:); N=Nc;
end
dt=ts(2)-ts(1); % Sampling interval
vo(1) = 0; % Initial value of the output voltage vo(t)
for n=1:N
    vD(n) = vi(n)-vo(n); iD(n) = iDv(vD(n)); iR(n) = vo(n)/R;
    iC(n) = iD(n) - iR(n); % Eq. (2.2.4b)
    vo(n+1) = vo(n) + iC(n)/C*dt; % Eq. (2.2.4a)
end
vo = vo(2:end); % To make the size of vo equal to that of vi
%elec02f09.m
% To simulate the rectifier in Fig. 2.9.1(a)
clear, clf
Vm=5; f=60; w=2*pi*f; P=1/f; % Amplitude, Frequency, Period of vi(t)
R=1e4; C=5e-6; % Values of R and C of the RC filter
dt=1e-5; t=0:dt:0.04; vi=Vm*sin(w*t); % Time range, Input voltage vi(t)
Is=1e-14; % Saturation current
vo=rectifier_RC([vi; t],R,C,Is);
subplot(313), plot(t,vi,'g', t,vo,'r')
N1=floor(P/dt); nn0=1:N1;
[VH,imax]=max(vo(nn0)); VH % The 1st peak value of vo(t)
tH1=t(imax); % The 1st peak time
N2=2*N1+10; nn1=N1:N2;
[VL,imin]=min(abs(vo(nn1))); VL
tL1=t(N1-1+imin); % The 1st valley time
[emin,imin]=min(abs(vo(nn1)-VH));
tH2=t(N1-1+imin); % The 2nd peak time
TF=tL1-tH1, TR=tH2-tL1 % Falling/Rising period



>>elec02f09
 VH = 4.3567 % Upper limit (High value) of the output voltage
 VL = 3.2586 % Lower limit (Low value) of the output voltage
 TF = 0.0147 % Falling time
 TR = 0.0020 % Rising time
 


Figure 2.9.2 Input/output voltage waveforms of the half‐wave rectifier.


These results are close to those obtained via an analytical approach or the PSpice simulation results depicted in Figure 2.9.1(d).
One observation about the behavior of the output voltage v_o(t) made from Figures 2.9.1(d) or 2.9.2 is that v_o(t) follows the input voltage v_i(t) = V_msin (ωt) = 5 sin (2πft) (f = 60 Hz) promptly when rising up, but very lazily when falling down, which is helpful for making the rectifier output v_o(t) smooth with a small ripple. Why are the behaviors of the circuit different for the two cases of the capacitor being charged and discharged? It is because the time constant of the circuit with the capacitor being charged (via the diode) from the source is much shorter than that with the diode off and the capacitor being discharged, as can be seen from the equivalent circuits with the diode ON/OFF depicted in Figure 2.9.1(b) and (c):


(cf.) This kind of circuits can be used not only for rectifying and smoothing an AC voltage into a DC voltage in power supplies, but also for demodulating a conventional amplitude modulated (AM) signal to restore the message signal in communication systems.



2.2.5 Full‐wave Rectifier
Figure 2.10(a1) and (a2) shows a full‐wave rectifier using a center‐tapped transformer and another full‐wave rectifier using a diode bridge, respectively.


Figure 2.10 Two full‐wave rectifiers and their voltage transfer characteristics (VTCs), output voltage waveforms, and peak inverse voltages (PIVs).


Figure 2.10(b1) and (b2) shows their input‐output relationships, called voltage transfer characteristic (VTC):
(2.2.5a) 
(2.2.5b) 
Figure 2.10(c1) and (c2) shows their PSpice simulation results (obtained from the Transient analysis with v_i(t) = V_m sin (2πt) (V_m = 5 V)) for the output voltage v_o(t) and a reversed diode voltage −v_D(t), from which we see their PIVs for a diode as
(2.2.6a) 
(2.2.6b) 


2.2.6 Full‐wave Rectifier with LC Filter
Figure 2.11(a) shows the PSpice schematic of a rectifier circuit in which a full‐wave rectified voltage v_i(t) = |10 sin (2π60t)| is made smooth by an LC low‐pass filter as can be observed from the input and output signals and their spectra in Figure 2.11(b) and (c), respectively. We are going to find the condition on LC (with R = 10 kΩ) that should be satisfied to keep the relative magnitude of the major harmonic component to the DC component less than r_max, say, 5%. To this end, we will perform the Fourier analysis to find the two leading frequency components (including the DC term) of the input v_i(t) and output v_o(t).
Since the input voltage v_i(t) to the LC filter is a full‐wave rectified cosine wave, we can use (E1.5.7) (in Example 1.5) to write its Fourier series representation as


Figure 2.11 PSpice simulation of a full‐wave rectifier (“rectifier_fullwave.opj”).


(2.2.7)
The transfer function and frequency response of the LCR filter are
(2.2.8) 
Thus, the magnitudes of the DC component and the first harmonic in the output are
(2.2.9) 
(2.2.10) 
Consequently, we can write the condition on LC (with R = 10 kΩ) for the relative magnitude of the major harmonic to the DC component to be less than r_max as
(2.2.11) 
It seems to be good to determine the admissible region for (C, L) satisfying the design specification on filtering off harmonics with r_max = 5 and 10%. This can be done by saving Eq. (2.2.11) in an M‐file named ‘elec02f12_f.m’ and running the following MATLAB script “elec02f12.m” that uses the nonlinear equation solver ‘fsolve()’ to solve Eq. (2.2.11) for L at different values of C in some range and plot the C-L curves for r_max = 5 and 10% as shown in Figure 2.12. Note that the region below the curves in Figure 2.12 is not admissible in the sense that no positive values of (C, L) in the region can satisfy the above inequality constraint (2.2.11).


Figure 2.12 Admissible region for (C, L) to satisfy the design specification on the relative magnitude of the major harmonic to the DC component.






%elec02f12.m
clear, clf
global R w0
R=1e4; w0=2*pi*60;
CC=logspace(-7,-3,100); % Range of C to 100 points on [10^-7,10^-3]
ftn='elec02f12_f'; gss='brgm'; % The function to solve
ratioms=[0.05 1];
for i=1:numel(ratioms)
 for m=1:length(CC)
    C= CC(m); % Given the value of C
    if m<2, L0=10; else L0=LL(m-1); end % Initial guess of L
    LL(m)= fsolve(ftn,L0,optimset('Display','off'),C,ratioms(i));
 end
 loglog(CC,LL,gss(i)), hold on
end
plot(1e-6,50,'mo'); axis([CC([1 end]) 1e-3 1e3]);
xlabel('C'); ylabel('L')
function y=elec02f12_f(L,C,r_max)
global R w0
w=2*w0; y= (1-w^2*L*C)^2 + (w*L/R)^2 - (2/3/r_max)^2; % Eq. (2.2.11)






2.2.7 Precision Rectifiers
Figure 2.13(a) shows a basic precision half‐wave rectifier circuit, which consists of an OP amp (having a diode in its negative‐feedback path) and a resistor where the OP amp output voltage v_o0 is basically determined as A(v₊ − v₋) = A(v_i − v₋) (A: the open‐loop gain) unless it exceeds the saturation voltage ±V_om (Eq. (5.1.1) in Section 5.1). How will it work? Let us assume that the diode is off so that no current flows through R and thus v₋ = 0.




Case 1

When v_i = v₊ > 0,
v_o0 will go positive to make v_D = v_o0 − v₋ > 0 so that the forward‐biased diode will conduct. This will make a closed feedback path between the output and the negative input terminal of the OP amp so that by the virtual short principle (Remark 5.1),
(2.2.12a) 







Case 2

When v_i = v₊ < 0,
v_o0 will go negative to make v_D = v_o0 − v₋ < 0 so that the reverse‐biased diode will be cut off. Thus, no current will flow through R, causing
(2.2.12b) 
where the negative feedback is broken up so that the output voltage v_o0 of the OP amp operating in the open‐loop mode will go to the negative saturation voltage −V_om.





Figure 2.13 The basic precision half‐wave rectifier, called a “superdiode.”


Figure 2.13(b) shows the input-output relationship (solid line), called VTC, of the half‐wave rectifier circuit based on Eq. (2.2.12a,b). Note that it does not have the threshold voltage V_D unlike that (dotted line) of the simple half‐wave rectifier circuit in Figure 2.8(a) and that is why such a combination of a diode with an OP amp may well be called a “superdiode” with V_D = 0. Isn't it marvelous? Now, let us see some improved versions of this basic precision rectifier.

2.2.7.1 Improved Precision Half‐wave Rectifier
Figure 2.14(a) shows an improved precision half‐wave rectifier circuit. Let us see how it works.



Case 1

When v_i > 0,
v_o0 (desiring to be A(v₊ − v₋) ~ −Av_i) will go negative to make  = v₋ − v_o0 > 0 so that the forward‐biased diode D₁ will conduct. This will make a closed feedback path via D₁ between the output and the negative input terminal of the OP amp so that by the virtual short principle, v₋ ≈ v₊ = 0 V (virtual ground) and thus v_o0 = v₋ −  = v₋ − V_D = −V_D (clamped at one diode drop below zero), keeping D₂ off. Then no current flows through R₂ so that
(2.2.13a) 







Case 2

When v_i < 0,
v_o0 will be positive to forward bias D₂ (through R₂-R₁-v_i) and reverse bias D₁ (with ) so that D₁/D₂ will be off/on, respectively. Then a negative feedback path is established through D₂-R₂ so that by the virtual short principle, v_‐ ≈ v₊ = 0 V and thus
(2.2.13b) 
This causes  so that the reverse‐biased D₁ can be kept off. Note that whether v_i > 0 or v_i < 0, a negative feedback path is maintained so that time required to bring the OP amp out of saturation (when the sign of v_i changes from – to +) can be saved.



Figure 2.14(b) shows the input-output relationship, called VTC, of the half‐wave rectifier circuit based on Eqs. (2.2.13a) and (2.2.13b). The PSpice simulation results (obtained from the Transient analysis with v_i(t) = V_m sin (2πt) (V_m = 5 V)) of the two precision half‐wave rectifiers in Figures 2.13(a) and 2.14(a) for the output voltage v_o(t) and a reversed diode voltage −v_D(t) are shown in Figure 2.15(a) and (b). From the graphs, we see their PIVs for a diode as


Figure 2.14 An improved (fast) precision half‐wave rectifier.




Figure 2.15 Simulation results of two precision half‐wave rectifiers (“elec02f15a.opj,” “elec02f15b.opj”).


(2.2.14a) 
(2.2.14b) 
where V_m and V_om are the maxima of the input voltage v_i(t) and OP amp output voltage v_o0(t), respectively.



2.2.7.2 Precision Full‐wave Rectifier
Figure 2.16.1(a) shows a precision full‐wave rectifier circuit, which consists of a precision half‐wave rectifier, called a “superdiode” (Figure 2.13(a)), in the upper part and another precision half‐wave rectifier with an inverting OP amp circuit (Figure 2.14(a)) in the lower part. When v_i = v₊₁ > 0, the upper part lets the input v_i pass and when v_i = v₋₂ < 0, the lower part inverts the input v_i with gain −R₂/R₁ (see Eq. (6.2.8)). Therefore, as shown in Figure 2.16.1(b), the VTC of this rectifier is
(2.2.15) 
Figure 2.16.2(a) shows another precision full‐wave rectifier circuit, which consists of a “superdiode” (Figure 2.13(a)) (with an additional capacitor C in parallel with diode D₁) in the left part and an inverting OP amp circuit (with diode D₁ connected to its positive input terminal) in the right part. Note that the two OP amps U₁/U₂ have negative feedback through C/R₂ so that by the virtual short principle, we always have v₋₁ ≈ v₊₁ = v_i and v₋₂ ≈ v₊₂. Let us see how it works:



Case 1

When v_i = v₊₁ > 0,
v_o1 (desiring to be A(v₊₁ − v₋₁)) will be high enough to make D₁ off (with  = v₋₁ − v_o1 < V_TD) and D₂ on (with  = v_o1 − v₊₂ = V_D) so that v_o will be
(2.2.16a) 
where no current flows through R₁‐R₂ since C as well as D₁ will not conduct once it has instantly been charged to v_C = v₋₁ − v_o1 = v₊₂ − v_o1 = − = −V_D.


Figure 2.16.1 A precision full‐wave rectifier.









Case 2

When v_i = v₊₁ ≈ v₋₁ < 0,
v_o1 will be low enough to make D₁ on (with  = v₋₁ − v_o1 = V_D) and D₂ off (with  = v_o1 − v₊₂ < V_TD) so that i_R3 = 0 and thus v₋₂ ≈ v₊₂ =R₃i_R3 = 0. Then the OP amp U₂ together with R₁ and R₂ functions as an inverting amplifier with gain −R₂/R₁ (see Eq. (5.2.8)) so that
(2.2.16b) 
where C as well as D₂ will not conduct once it has instantly been charged to v_C =  = V_D.
Therefore, the VTC of this rectifier can also be described by Eq. (2.2.15) or Figure 2.16.2(b), which is identical to Figure 2.16.1(b).
How do the two precision full‐wave rectifiers compare with? First, the input impedance (seen from v_i) of the latter is much larger than that (R₁) of the former. Second, the PIVs of D₁ and D₂ in the latter (where the OP amps never enter the saturation region) are V_m + V_D in common, while those in the former (where the OP amps enter the negative saturation region when the diode in their negative feedback paths is off) are as high as max{−v_Di(t)} = V_m + V_om in common where V_m and V_om are the maxima of the input voltage v_i(t) and OP amp output voltage v_o0(t), respectively. From the PSpice simulation results shown in Figure 2.17, we see that the PIVs of the diodes in the two rectifiers are
(2.2.17a) 
(2.2.17b) 


Figure 2.16.2 A precision full‐wave rectifier with high input impedance [E-2, J-2, W-8].




Figure 2.17 PSpice simulation of the two precision full‐wave rectifiers (“elec02f17_1.opj,” ”elec02f17_2.opj”).








2.2.8 Small‐Signal (AC) Analysis of Diode Circuits
Consider the circuit with the PSpice schematic of Figure 2.18.1(a) where the PSpice Model for the diode D1N4148 (opened by selecting the diode and clicking on Edit>PSpice Model from the top menu bar) is shown in Figure 2.18.1(b). For PSpice simulation with the schematic, we do the following:

Fill in the Simulation Settings dialog box (for Transient or Bias_Point analysis) as shown in Figure 2.18.1(c) and click OK to close the dialog box.
Place a Current Marker to measure the diode current i_D(t) and click Run to get the waveform of i_D(t) as shown in Figure 2.18.1(d) or the bias point analysis on the schematic or in the output file.

To get the v-i characteristic of the diode and draw the load lines in the PSpice A/D Window, we do the following:


Figure 2.18.1 Simulation of a diode circuit driven by a DC source and an AC source (“e lec02f18.opj”).



Construct the PSpice schematic as Figure 2.18.2(a)
Fill in the Simulation Settings dialog box for DC Sweep analysis (Figure 2.18.2(b)) and click Run.
Click Trace>Add Trace from the top menu bar to open the Add Traces dialog box and fill in the box as Figure 2.18.2(e), which yields the load lines (Figure 2.18.2(c)).



(Q) Can the waveform of i_D(t) (Figure 2.18.1(d)) be predicted from the Q‐points in Figure 2.18.2(c)?

To determine the diode constants of the diode D1N1418, we can use the curve fitting toolbox ‘cftool’ (in MATLAB) to fit the data points (v_D, i_D) of the v-i characteristic curve (Figure 2.18.2(c)) to the Shockley diode equation. Noting that curve fitting works better for linear functions than for nonlinear functions, let us approximate the Shockley diode equation and take the logarithms of both sides to linearize as


Figure 2.18.2 PSpice simulation to get the v-i characteristic and operating point(s) for (“elec02f18b.opj”).


(2.39)
To determine the parameters 1/ηV_T and ln I_S of Eq. (2.2.18) which fit the PSpice simulation data, do the following:

Select I(D1) below the current waveform graph (Figure 2.18.2(c)), press ‘CTRL+c’ (copy), and then press ‘CTRL+v’ (paste) into a notepad to create a data file named ‘vD_iD.dat’ (Figure 2.18.2(d)) where the first line containing the variable descriptions should be deleted.
Run the following MATLAB statements:

  >>load vD_iD.dat, vD=vD_iD(:,1); iD=vD_iD(:,2);
 ln_iD=log(iD); % Take natural logarithm to linearize fitting ftn
 cftool % To start the curve fitting toolbox


This will open the CFTOOL window as shown in Figure 2.18.3(a).

Click  button to open the Data dialog box (Figure 2.18.3(b)).
In the Data dialog box, put ‘vD’ and ‘ln_iD’ into the fields of X Data and Y Data, respectively, and click  button to create a new data set named ‘ln_iD vs. vD’.
Click  button to open the Fitting dialog box (Figure 2.18.3(c)).
In the Fitting dialog box, select ‘ln_iD vs. vD’ and ‘Custom Equations’ in the fields of 
Data set and 
Type of fit, respectively.
Click  button inside Custom Equations panel to open a New Custom Equation dialog box.
In the New Custom Equation dialog box, click the tab 
General Equations and construct the model equation corresponding Eq. (2.2.18) as

 y = a*x +ln_Is

where a and ln_Is stand for 1/ηV_T and ln I_S, respectively. Then click  button to close the New Custom Equation dialog box.
In the Fitting dialog box, click  button to make the following results appear in the box below 
Result:



Figure 2.18.3 Using cftool for curve fitting to determine the diode constants.




 


Coefficients (with 95% confidence bounds):
 a = 21.24 (20.87, 21.6)
 ln_Is = -19.72 (-19.88, -19.56)




This implies that the parameters ηV_T and I_S have been determined as
(2.2.19) 
where the true values of ηV_T and I_S can be found from the PSpice Model of the diode (Figure 2.18.1(b)) as
(2.2.20) 


(Q) Are the curve fitting results fine? To be honest with our readers, the accuracy of curve fitting depends on not only the number of measured data points but also the data range.






With the diode constants found in the corresponding PSpice Model Editor (Figure 2.18.1(b)) or obtained from the curve fitting (Figure 2.18.1(c)), let us make a theoretical analysis of the diode circuit (Figure 2.18.1(a)) by using the nonlinear equation solver ‘fsolve()’ of MATLAB to solve the (nonlinear) KCL equation
(2.2.21) 
for v_D(t) or to solve the (nonlinear) KVL equation
(2.2.22) 
for i_D(t). To do this job, we compose the MATLAB script “elec02f1804.m” as below and run it to get Figure 2.18.4, which shows the diode current waveform (plotted as blue line) together with those obtained from the PSpice simulation (Figure 2.18.1(d)) and the theoretical analysis.

(Q) How would you copy the PSpice simulation data (Figure 2.18.1(d)) into a MATLAB graph?



 


%elec02f1804.m
Vs=1; vd=0.1; % Amplitudes of DC/AC voltage sources
RL=50; % Load resistance
f=1000; w=2*pi*f; % Frequency of the AC source
Is=2.682e-9; nVT=0.0475; % Diode constants Eq. (2.2.20)
dt=1e-6; t=[0:1000]*dt; % Time range for solution
vst = Vs + vd*sin(w*t); % Source voltage waveform
% To solve Eq. (2.2.21) for vD and use Eq. (2.1.1) to find iD(t) from vD(t)
eq_2221=@(vD,Is,nVT,RL,vs)RL*Is*(exp(vD/nVT)-1)-vs+vD; % Eq. (2.2.21)
options=optimset('Display','off');
for n=1:length(t)
    vD0=0.7; vD(n)=fsolve(eq_2221,vD0,options,Is,nVT,RL,vst(n));
    iD(n)=Is*(exp(vD(n)/nVT)-1);
end
% To solve Eq. (2.2.22) for iD(t)
eq_2222=@(iD,Is,nVT,RL,vs)vs-nVT*log(iD/Is+1)-RL*iD; % Eq. (2.2.22)
for n=1:length(t)
    iD0=0.006; iD1(n)=fsolve(eq_2222,iD0,options,Is,nVT,RL,vst(n));
end
load t_iD.dat % iD(t) data from PSpice
t_PSpice=t_iD(:,1); iD_PSpice=t_iD(:,2);
VQ=695e-3; IQ=6.1e-3; % Operating point from Fig. 2.18.2(c)
% To find the dynamic distance rd
dvD=0.7-0.69; diD=0.00665690237656236-0.00552081875503063;
rd1=dvD/diD % Eq. (2.2.23a) using PSpice data in data file 'vD_iD.dat'
rd2=nVT/(Is+IQ) % Eq. (2.2.23b) using the Shockley diode equation
rd0=8.21; % from the output file obtained from Bias Point analysis
% To find iD(t) using the analytical expression Eq. (1.1.12)
iD2 = IQ+vd/(RL+rd0)*sin(w*t); % Eq. (1.1.12)
plot(t,iD, t,iD1,'m:', t_PSpice,iD_PSpice,'g', t,iD2,'r'), grid on, shg
legend('fsolve vD-iD','fsolve iD-vD','PSpice','Eq. (1.1.12) with rd0')






Now, to get an overview of the input-output relationship of the diode circuit, let us perform a (theoretical) small‐signal analysis by using Eqs. (1.1.12) and (1.1.13). First, we get the operating point Q as (V_Q, I_Q) = (0.695, 0.0061) from the intersection of the (major) load line and the v-i characteristic curve in Figure 2.18.2(c). Then, we find the dynamic resistance r_d by reading REQ = 8.21 from the Bias Point analysis result shown in the output file (Figure 2.18.1(d)) or by using the PSpice data (stored in the data file ‘vD_iD.dat’) or Eq. (2.1.5) as follows:


Figure 2.18.4 Diode current waveforms obtained in various ways.


(2.2.23a)
(2.2.23b) 
Which one of the three values [8.21 (from PSpice Bias Point analysis), 8.80 (from PSpice simulation data), 7.79 (from the theoretical formula)] should we use for Eqs. (1.1.12) and (1.1.13)? The authors have no idea. How about 8.21 close to their average? Thus, we use Eqs. (1.1.12) and (11.13) with r_d = 8.21 to write the theoretical equation for the diode currents/voltages as
(2.2.24) 
(2.2.25) 
This diode current waveform with r_d = 8.21 is depicted together with the ones obtained in other ways in Figure 2.18.4. The diode current waveforms are expected to become closer to each other if the magnitude v_δ of AC voltage is smaller so that the approximation of the v-i characteristic curve by its tangent line at Q‐point can become more accurate.


2.3 Zender Diodes
Figure 2.19(a) and (b) shows the symbol and the v-i characteristic for a special kind of diode, called a Zener diode where v_Z = −v_D and i_Z = −i_D. A Zener diode behaves as other normal diodes in the forward‐bias mode but, in the reverse‐bias mode, withstands the reverse diode current (up to I_Z,max) while keeping v_Z = −v_D close to the Zener (breakdown) voltage V_Z (even with some variation in its current i_D) as long as i_Z = −i_D remains between I_Z,min and I_Z,max. The maximum reverse current I_Z,max that the diode can endure is P_Z,max/V_Z where P_Z,max is the maximum power dissipation. The minimum reverse current I_Z,min needed to keep the diode in the reverse breakdown mode is slightly below the Zener knee current I_ZK, at which the diode exhibits the reverse breakdown. The v-i characteristic curve of a Zener diode in terms of its static behavior can be approximated by a red/brown PWL line for the forward‐/reverse‐bias mode as depicted in Figure 2.19(b) where the diode resistance r_f (in the forward‐bias mode) and the Zener resistance r_z (in the reverse‐bias mode) are defined as


Figure 2.19 Symbol, v-i characteristic, and PWL model of a Zener diode.


(2.48)
(2.3.1b) 
Here, −V_Z0 is the diode voltage at the intersection of the straight line having slope 1/r_z with the voltage axis and it is almost equal to the Zener knee voltage −V_ZK. According to the approximation, the v-i characteristic of a Zener diode in the forward‐/reverse‐bias mode is represented by the equivalent model depicted in Figure 2.19(c).
Figure 2.20(a) shows a Zener (shunt) regulator, which is supposed to maintain an almost constant output voltage for all the variation of the DC voltage source v_s and the load resistor R_L. In order for the regulator to function properly in the breakdown region, the Zener diode current i_Z should be bounded as
(2.3.2) 
Thus, the source resistance R_s should satisfy the following inequality:
(2.3.3) 
If I_Z,max = P_Z,max/V_Z has not yet been specified, R_s can be set to some value slightly less than the upper bound of Inequality (2.3.3):
(2.3.4) 


Figure 2.20 Zener (shunt) regulator.


If R_s is fixed, the minimum load resistance can be determined by substituting V_Z = V_ZK and i_Z = I_ZK into Inequality (2.3.3) as
(2.3.5) 
Then the power rating of the Zener diode should be determined so that the following inequality can be satisfied:
(2.3.6) 
Figure 2.20(b) shows the Zener regulator with the Zener diode represented by the reverse bias model (Figure 2.19(c)), for which we can apply KCL at node 1 to write the node equation in v_Z as
(2.3.7) 
This can be solved for v_Z to yield
(2.3.8) 
According to this (approximate) expression of v_Z, its variations w.r.t. v_s, R_L, and I_L are computed as
(2.3.9a) 
(2.3.9b) 
(2.3.9c) 
This implies that the sensitivities of v_Z w.r.t. v_s/R_L become better (smaller) as R_s/R_L increases, respectively.
Note that if v_Z < V_Z0 so that i_Z = (v_Z − V_Z0)/r_z < 0, we set i_Z = 0(I_ZK) and use the voltage divider rule to determine v_Z as if there were no Zener diode branch:
(2.3.10)  
The following MATLAB function ‘Zener_regulator()’, given the values of V_Z, I_Z, r_Z, I_ZK, R_L, R_s, v_s, and dv_s (the variation of v_s) for a Zener regulator (shown in Figure 2.20(a)), returns the (output) voltage v_Z (across the Zener diode or load resistor) and the current i_Z through the Zener diode, together with the sensitivities of v_Z w.r.t. v_s, R_L, and I_L.




function [vZ,iZ,dvZdvs,dvZdRL,dvZdIL,Rsmax,RLmin,VZ0] =         Zener_regulator(VZ,IZ,rz,IZK,RL,Rs,vs,dvs)
% Input:  VZ = (Nominal) voltage across Z at the operating point
%         IZ = (Nominal) current through Z at the operating point
%         rz = Zener resistance
%        IZK = Zener knee current
%         RL = Load resistance
%         Rs = Source resistance
%         vs = Source voltage
%        dvs = Absolute variation of vs
% Output:vZ = Output voltage across Z||RL
%        iZ = Current through the Zener diode Z
% Copyleft: Won Y. Yang, wyyang53@hanmail.net, CAU for academic use only
if nargin<8, dvs = 0; end
Rsmax = (vs-dvs-VZ)./(VZ./RL+IZK); % Eq. (2.3.4)
VZ0 = VZ - rz*IZ; % Almost equal to the Zener knee voltage VZK
VZK = VZ0+rz*IZK; % Zener knee voltage
RLmin = VZK./((vs-dvs-VZK)/Rs-IZK); % Eq. (2.3.5)
N_RL=length(RL); N_vs=length(vs);
if N_RL<N_vs, RL=repmat(RL,1,N_vs); end
if N_vs<N_RL, vs=repmat(vs,1,N_RL); end
numerator = vs/Rs+VZ0/rz;
denominator = 1/Rs+1/rz+1./RL;
vZ = numerator./denominator; % Eq. (2.3.8)
iZ = (vZ-VZ0)/rz;
for n=1:length(iZ)
   if iZ(n)<0 % As if there were no Zener diode branch
    iZ(n) = 0; vZ(n) = RL(n)/(Rs+RL(n))*vs(n); % Eq. (2.3.10)
 end
end
dvZdvs = 1/Rs./denominator; % Eq. (2.3.9a)
dvZdRL = numerator./RL.^2./denominator.^2; % Eq. (2.3.9b)
dvZdIL = -dvZdRL.*RL.^2/VZ; % Eq. (2.3.9c)








Example 2.3 A Zener (Shunt) Regulator
Consider the Zener regulator shown in Figure 2.20(a), whose purpose is to keep the output voltage across R_L close to 4.7 V where the source voltage V_s and the load resistance R_L vary between 12 ± 2 [V] and between 200 and 1000 Ω, respectively. Let the values of the device parameters of the Zener diode Z (1N750) be
(E2.3.1) 
where the maximum and minimum currents for the Zener diode to function properly in the breakdown region are I_Z,max = P_Z,max/V_Z = 352.5[mW]/4.7[V] = 75[mA] and I_Z,min = 5[mA], respectively.

Use Eq. (2.3.3) to fix the value of the source resistance R_s:
(E2.3.2) 
Let us fix R_s as 180 Ω.
Use Eq. (2.3.1b) together with Eq. (E2.3.1) to determine V_Z0 for the PWL model (Figure 2.19(c)) of the Zener diode Z:
(E2.3.3) 
Use the equivalent circuit (Figure 2.20(b)) with the Zener diode Z replaced by its PWL model to find the output voltage v_o = v_Z (across R_L = 200 Ω in parallel with the Zener diode) to the source voltage v_s = 14, 12, and 8.5V.
We can use Eq. (2.3.8) to find v_o:
(E2.3.4) 
However, v_Z = 4.667 < V_Z0 = 4.67 [V] is not possible as long as the Zener diode Z is ON. Thus, we have to recalculate v_Z for v_s = 8.5V on the assumption that Z is OFF so that i_Z = 0 A. Then, as if there were no Zener diode branch, the voltage divider rule can be used to find v_Z as
(E2.3.5) 
Here, we can use the above MATLAB function ‘Zener_regulator()’ as


 


VZ=4.7; IZ=0.02; rz=1.5; IZK=1e-3;
Rs=180; RL=200; vss=[14 12 8.5]; dvs=14-12; [vos,iZ,dvodvs,dvodRL]=…Zener_regulator(VZ,IZ,rz,IZK,RL,Rs,vss,dvs)




Running this block of MATLAB statements yields

 vos =    4.7120  4.6957  4.4737
 iZ =     0.0280  0.0171       0
 dvodvs = 0.0082  0.0082  0.0082


(Q1) Are these values of the output voltage v_o close to the above results with the PWL model?
(Q2) Is the change of the output voltage v_o (from 4.696 to 4.712 V) due to that of the source voltage v_s by Δv_s = 2 V (from 12 to 14 V) predictable from the line regulation dv_o/dv_s = 0.0082?

Use the equivalent circuit (Figure 2.20(b)) with v_s = 12 V to find the output voltage v_o = v_Z for R_L = 200, 600, and 1000 Ω.
We can use Eq. (2.3.8) to find v_o:
(E2.3.6) 
Here, we can use the above MATLAB function ‘Zener_regulator()’ as




VZ=4.7; IZ=0.02; rz=1.5; IZK=1e-3; Rs=180; RLs=[200 600 1000]; vs=12; [vos,iZ,dvodvs,dvodRL]=Zener_regulator(VZ,IZ,rz,IZK,RLs,Rs,vs)




Running this block of MATLAB statements yields

 vos =     4.6957   4.7189  4.7236
 iZ =     0.0171   0.0326  0.0357
 dvodRL =  1.0e-03 * 0.1733  0.0195  0.0070


(Q1) Are these values of the output voltage v_o close to the above results with the PWL model?
(Q1) Is the change of the output voltage v_o (from 4.719 to 4.724 V) due to that of the load resistance R_L by ΔR_L = 400 Ω (from 600 Ω to 1 kΩ) predictable from dv_o/dR_L = 1.95 × 10⁻⁵? If not, why is that? How about Δv_o for a 10% change of R_L like ΔR_L = 60 Ω from R_L = 600 Ω?

PSpice Simulation
Figure 2.21(a) shows the PSpice schematic of the Zener regulator with V_s = 12 V and R_s = 180 Ω. Referring to Section H.5.4, do the DC Sweep and Parametric Sweep Analyses to get the plots of v_o versus v_s for different values {200, 400, …, 1000} of R_L as follows:

Click the value of R_L (to be varied) and set it to {Rvar} (including the curly brackets) in the schematic (Figure 2.21(a)).
Click the Place Part button on the tool palette in the Schematic window to open the Place Part dialog box, get PARAM (contained in the library ‘special.olb’), and click OK to place it somewhere in the schematic (Figure 2.21(a)).
Double‐click the 
PARAMETERS: placed in the schematic to open the Property Editor spreadsheet (Figure 2.21(b)) and click the New Column button to open the Add New Column box (Figure 2.21(c)), in which you can type Rvar and 100 into the Name and Value fields, respectively, where the numerical value entered as 100 here does not matter.
Click the New Simulation Profile button to create a new simulation profile named, say, ‘DC_sweep’, click the Edit Simulation Profile button to open the Simulation Settings dialog box, and fill it out as depicted in Figure 2.21(d), where the menu of Options is selected as Parametric Sweep, the Sweep variable is chosen to be Global parameter named ‘Rvar’, and the Sweep type is set to Linear with Start value 200, End value 1000, and Increment 200. If the values of parameters do not form an arithmetic progression (with constant difference), you may type the list of the parameter values (inside brackets) into the Value list field as illustrated in Figure 2.21(d). Then click OK to close the Simulation Settings dialog box.
Click the Voltage/Level Marker button to put the voltage probe pin at the output node, click the Run button to perform the simulation, and see the multiple curves of v_o versus v_s appearing in the PSpice A/D (Probe) Window as shown in Figure 2.21(e).
Now, to check if the (maximum) Zener diode current obtained with the largest value of RL = 1000 exceeds I_Z,max = 75 [mA], do the following:
Click the Current Marker button to put the current probe pin at the K(Cathode) node of the Zener diode, and see the multiple curves of i_Z versus v_s.
Click the rightmost one among the symbols for –I(D) to select the curve of i_Z for RL = 1000.
Click the Toggle Cursor button on the tool bar in the Probe window to have the cross‐type cursor appear, move it to the right end of the current waveform corresponding to v_s = 14 V, and read the value of i_Z = 46.664 [mA], which turns out to be less than I_Z,max = 75 [mA].



Figure 2.21 From PSpice schematic to simulation result for a Zener (shunt) regulator.



To determine the power rating of R_s, find the maximum power that can be dissipated by R_s.
(2.67)

Figure 2.22(a1) and (a2) show a symmetrical limiter using two Zener diodes and one using normal diodes, respectively, where Figure 2.22(b1) and b2 shows their input-output relationships called VTCs. Note that the upper/lower limits of the Zener limiter output are (V_TD + V_Z)/(₋V_TD − V_Z) (Figure 2.22(b1)) and those of the diode limiter output are (V_TD + V₁)/(−V_TD − V₂) (Figure 2.22(b2)).


Figure 2.22 A limiter using Zener diodes and two ones using normal diodes (“Zener_limiter.opj,” “Diode_limiters.m”).


Figure 2.22(a3) and (b3) shows an asymmetrical limiter using two D_i -V_i -R_i paths (i = 1, 2) in parallel, and its input‐output relationship, respectively. Note that the slopes of the input‐output relationship above the point (V_D+V₁, V_D+V₁) and below the point (−V_D−V₂, −V_D−V₂) are determined as the voltage divider gain of the circuit with the diodes and voltage sources removed by short‐circuiting:
(2.3.11) 
To analyze this limiter based on the exponential model (Eq. (2.1.1)) for the diodes, we can apply KCL at nodes 1, 2, and 3 to write a set of node equations:
(2.3.12) 
where  and use the MATLAB function ‘fsolve()’ to solve it as listed in the following MATLAB script “diode_limiters.m.”




%diode_limiters.m
% Copyleft: Won Y. Yang, wyyang53@hanmail.net, CAU for academic use only
clear, clf
Is=10e-15; % Saturation current
VT=(273+27)/11605; % Thermal voltage
iD = @(vD)Is*(exp(vD/VT)-1); % Eq. (2.1.1a)
options = optimset('TolFun',1e-10, 'Display','off');
vs = [-12:0.05:12]; % Range of the source voltage signal
Rs=1e4; R1=1e4; R2=2500; V1=4.7; V2=4.7;
v=zeros(length(vs),3); % Initialize the voltage values to zero
for n=1:length(vs)
  eq = @(v)[(vs(n)-v(1))/Rs-iD(v(1)-v(2))+iD(v(3)-v(1));
            iD(v(1)-v(2))-(v(2)-V1)/R1;
            iD(v(3)-v(1))+(v(3)+V2)/R2]; %Eq. (2.3.12)
 if n<2, v0 = [0 0 0]; else v0 = v(n-1,:); end
 v(n,:) = fsolve(eq,v0,options);
end
Vsm=12; VD=0.7; VD1=VD+V1; VD2=VD+V2;
plot(vs,v(:,1), [VD1 VD1 Vsm],[0 VD1 VD1+(Vsm-VD1)*R1/(Rs+R1)],'m:', ...
 [-Vsm -VD2 -VD2],[-VD2-(Vsm-VD2)*R2/(Rs+R2) -VD2 0],'m:') %Eq. (2.3.11)







Problems

2.1 Diode Circuits

Consider the diode circuit of Figure P2.1.1(a1) where there are four possible states for the two diodes D₁ and D₂: ON-ON, ON-OFF, OFF-ON, and OFF-OFF.
First, assuming that both D₁ and D₂ are ON, replace them by the Constant Voltage Drop (CVD) model (with V_D = 0.7 V) to draw the equivalent as shown in Figure P2.1.1(a2), find the currents  and , and check the validity of the solution.

For a more exact analysis using the (nonlinear) exponential model (2.1.1) with I_s = 1 × 10^‐14[A] and V_T = (27 + 273)/11605[V], apply Kirchhoff's current law (KCL) at nodes 1 and 2 to write two node equations as
(P2.1.1) 
and use the MATLAB function ‘fsolve()’ to solve them for v₁ and v₂. To this end, complete the following MATLAB script “elec02p01a.m” and run it to find v₁, v₂, , and .


Figure P2.1.1 Diode circuits for Problem 2.1.




 


%elec02p01a.m
clear, clf
T=27; nVT=(T+273)/11605; % Temperature[Celsius] and Thermal voltage
Is=1e-14; % Leakage current of the diodes
% Diode exponential model parameters
iD = @(vD)Is*(exp(vD/VT)-1); % Eq. (2.2.1a)
R1=5e3; R2=10e3; % Circuit parameter values
eq = @(v)[iD(-v(?))+iD(v(2)-v(?))-(v(?)+10)/R1; ...
          iD(v(?)-v(1))-(10-v(?))/R2];
v0 = [0; 0]; % Initial guess of [v1; v2]
options=optimset('Display','off', 'TolX',1e-10, 'TolFun',1e-10);
v = fsolve(eq,v0,options); % Solving the set of nonlinear eqs
ID1 = iD(-v(1)); ID2 = iD(v(?)-v(?));
fprintf(' ID1=%8.3fmA, ID2=%8.3fmA, V1=%8.4fV, V2=%8.4fV\n', ID1*1e3,ID2*1e3,v(1),v(2));







Consider the diode circuit of Figure P2.1.1(b1).

First, assuming that both D₁ and D₂ are ON, replace them by the CVD model (with V_D = 0.7 V) to draw the equivalent as shown in Figure P2.1.1(b2) and find the currents  and . If the solution turns out to be invalid, try with another assumption.
For a more exact analysis using the (nonlinear) exponential model (2.1.1) with I_S = 6 × 10^‐16 A, make a slight modification of the above MATLAB script “elec02p01a.m” and run it to find v₁, v₂, , and .

Perform the PSpice simulation of the diode circuit of Figure P2.1.1(a1) with the Analysis type of Bias Point by taking the following steps:

Compose the PSpice schematic as shown in Figure P2.1.2(a).
Create a simulation profile (with the analysis type of Bias Point) by selecting ‘Bias Point’ as the analysis type in the Simulation Settings dialog box as shown in Figure P2.1.2(b).


Run the PSpice schematic and click on the ‘Enable Bias Voltage Display’/‘Enable Bias Current Display’ button in the toolbar of the Capture CIS Window to see the bias‐point analysis results on voltages/currents at/through each node/branch.
2.2 Bridge Rectifier Circuit
Consider the bridge rectifier circuit of Figure P2.2(a) consisting of four diodes. Based on the (nonlinear) exponential model (2.1.1) with I_s = 1 × 10⁻¹⁴[A] and V_T = (27 + 273)/11605[V], apply KCL at nodes 1 and 2 to write two node equations as


Figure P2.1.2 PSpice simulation for the circuit of Figure P2.1.1(a1) – “elec02p01.opj.”




Figure P2.2 A bridge rectifier circuit and its analysis results for Problem 2.2.


(P2.2.1) 
and use the MATLAB function ‘fsolve()’ to solve them for v₁ and v₂ where v_s(t) = 5 sin (2πt) [V]. To this end, complete the following MATLAB script “elec02p02.m” and run it to plot v_s(t), v_o(t) = v₂(t), and − (the reverse




%elec02p02.m
Is=1e-14; T=27; VT=(T+273)/11605; % Device parameters
R=1e3; Vm=5; f=1; w=2*pi*f; % Circuit parameters
t=[0:1e-3:2]; vs=Vm*sin(w*t); vst=[vs; t];
[v1s,vos]=bridge_rectifier(vst,R,Is,VT);
plot(t,vs, t,vos, t,vos-v1s,'m')
function [v1s,v2s]=bridge_rectifier(vst,R,Is,VT)
vs=vst(1,:); t=vst(2,:);
iD=@(vD)Is*(exp(vD/VT)-1);
options=optimoptions('fsolve','Display','none');
for n=1:numel(t)
 vsn=vs(n);
 eq=@(v)[iD(v(1)-v(?))+iD(v(?)-vsn-v(2))-iD(-v(?))-iD(vsn-v(1));
         iD(v(?)-v(2))+iD(v(1)-vsn-v(?))-v(2)/R]*1e6;
 if n<2, v0=[0.7 0]; else v0=v; end
 v=fsolve(eq,v0,options);
 v1s(n)=v(1); v2s(n)=v(2);
end




voltage of diode D₂). Compare the waveforms with the PSpice simulation results shown in Figure 2.10c2.

2.3 Diode Clipping Circuits – Diode Limiters




%clippers.m
% Copyleft: Won Y. Yang, wyyang53@hanmail.net, CAU for academic use only
Is=10e-15; VT=25e-3; % Saturation current, Thermal voltage
iDvD = @(vD)Is*(exp(vD/VT)-1).*(vD>0);
iZvZ = @(vD,VZ0,rz)Is*(exp(vD/VT)-1).*(vD>0)-max (-VZ0-vD,0)/rz;
vZiZ = @(iD,VZ0,rz,IZK)VT*???(iD/Is+1).*(iD>0) +... % Eq. (P2.3.1)
        (VZ0/???)*iD.*(-IZK<=iD&iD<0)-(iD<-IZK).*(VZ0-??*iD);
options = optimset('TolFun',1e-10, 'Display','off');
% Symmetrical diode limiter
vi=[-10:0.05:10]; % Range of the input signal
Rs=1e3; V1=2; V2=-2;
vo=zeros(size(vi)); % Initialize the output voltage values to zero
for n=1:length(vi)
   eq = @(vo)(vi(n)-??)/Rs-iDvD(??-V1)+iDvD(V2-??);
   if n<2, vo0=0; else vo0=vo(n-1); end
   vo(n) = fsolve(eq,vo0,options);
end
subplot(331), plot(vi,vo)
% Symmetrical Zener limiter
vi=[-10:0.05:10]; % Range of the input signal
VZ0=4.67; IZK=4e-12; VZ=4.7; IZ=2e-3; rz=(VZ-VZ0)/IZ % Eq. (2.3.1b)
vo=zeros(size(vi)); % Initialize the output voltage values to zero
for n=1:length(vi)
   eq=@(i,VZ0,rz,IZK)vZiZ(?,VZ0,rz,IZK)-vZiZ(-?,VZ0, rz,IZK)                                   +Rs*?-vi(n);...
   if n<2, i0=-1; else i0=i(n-1); end
   i(n) = fsolve(eq,i0,options,VZ0,rz,IZK); vo(n) = vi(n)-Rs*i(n);
end
subplot(332), plot(vi,vo)
% To plot the v-i characteristic curve of a Zener diode
i=[-5:0.01:1]*1e-3; vz=vZiZ(i,VZ0,rz,IZK);
subplot(333), plot(vz,i, [-5 1],[0 0],'k', [0 0], i([1 end]),'k')




Consider the two diode clipping circuits (called limiters or clippers) each in Figure P2.3.1(a1) and (a2) where V_T = 25 mV, the reverse saturation current of the diodes is I_s = 10⁻¹⁴ A, and the Zener diode has V_Z = 4.67/4.7 V at I_Z = 0/2mA and I_ZK = 4 × 10⁻¹² A. Note that Figure P2.3.1(b1) and (b2) (obtained from PSpice simulation with Transient analysis) show their output voltage waveforms to sinusoidal input voltage of frequency 1 Hz and amplitude 5 V and 10 V, respectively, and Figure P2.3.1(c1) and c2 (obtained from PSpice simulation with DC sweep analysis and voltage source VSIN replaced by VDC) show their input-output relationships called voltage transfer characteristics (VTCs).


Figure P2.3.1 Diode clipping circuits (diode limiters) for Problem 2.3.



Referring to Figure 2.19, complete the following equation describing the typical v-i characteristic of a Zener diode, which has been piecewise linear (PWL) approximated in the reverse‐biased region:
(P2.3.1) 
Complete the sixth to seventh lines of the above MATLAB script “clippers.m” to create a MATLAB function handle defining the function v_Z(i_Z) with three parameters V_Z0, r_Z, and I_ZK where (iZ>0), (‐IZK<=iZ&iZ<0), and (iZ<‐IZK) are logical expressions, each of which becomes 1 or 0 depending on whether it is true or not. Then noting that V_Z0 = 4.67 V, use Eq. (2.3.1b) to determine the Zener resistance r_Z and plot the v-i characteristic of the Zener diode, i.e. i_Z versus v_Z for i_Z = (−5:0.01:1) × 10⁻³ [A] as shown in Figure P2.3.2(a) by running the last two lines of “clippers.m.”
To plot the v‐i characteristic (Figure P2.3.2(c)) of the Zener diode through PSpice simulation with DC sweep analysis, do the following:

Create a PSpice schematic shown in Figure P2.3.2(b1) where the device parameters of the Zener diode part ‘DbreakZ’ are set in the PSpice Model Editor (opened by clicking on that part so that it will be highlighted in pink and selecting the menu Edit>PSpice Model) as shown in Figure P2.3.2(b2).


Figure P2.3.2 The v-i characteristic curve of the Zener diodes in Figure P2.3.1(a2).


Click on New Simulation Profile button to open the Simulation Setting dialog box where you are supposed to set the Analysis type (DC Sweep), Sweep variable (Voltage source: Vi), and Sweep type (Linear: Start/End value = −4.8/0.8, Increment = 0.01) appropriately.
Place a current marker at the anode of the Zener diode and run the PSpice schematic to see the VTC as shown in Figure P2.3.2(c).

Write the KCL equation in v_o for node 1 in the clipper of Figure P2.3.1(a1) and the KVL equation in i for the mesh in the clipper of Figure P2.3.1(a2). With those equations, complete the above MATLAB script “clippers.m” so that it can plot the VTC curves of the two clippers. Run it to plot the VTCs and see if they are close to those shown in Figure P2.3.1(c1) and (c2).


2.4 Diode Clampers – DC Restorers
Consider the two diode clampers in Figure P2.4(a1) and (a2) that are driven by a PWL voltage source generating a square wave with magnitude ±5 V and period 2 s. Perform PSpice simulations of the clampers (with the SKIPBP box checked in the Simulation Settings dialog box) to get their input/output voltage waveforms as shown in Figure P2.4(b1) and (b2). Do their input-output relationships conform with Eqs. (2.2.1a) and (2.2.1b)?


Figure P2.4 Two clamper circuits and their PSpice simulation results (“dc:restorer.opj”).


2.5 MATLAB and PSpice Simulations of Voltage Doubler and Quadrupler




%voltage_doubler.m
Is=2.682e-9; T=27; nVT=1.836*(273+T)/11605; % Diode constants
iDv=@(vD)Is*(exp(vD/nVT)-1);
dt=0.001; tf=10; ts=0:dt:tf; Vm=5; f=2; w=2*pi*f; vs=Vm*sin(w*ts);
C1=1e-6; C2=1e-6; vC1(1)=0; vC2(1)=0;
for n=1:length(ts)
  vD1(n)=v?(n)-vC?(n); iD1(n)=iDv(vD1(n));
  vD2(n)=-vC?(n)-vD?(n); iD2(n)=iDv(vD2(n));  iC1(n)=iD?(n)-iD?(n);
  vC1(n+1) = vC1(n) + iC?(n)/C1*dt;
  vC2(n+1) = vC2(n) + sgn*iD?(n)/C2*dt;
end
plot(ts,vs,'r', ts,-vC2(1:end-1),'g'); grid on; legend ('vs(t)','vo(t)')




Consider the voltage doubler/quadrupler circuits driven by a sinusoidal voltage source of amplitude 5 V and frequency 2 Hz, whose PSpice schematics are shown in Figures P2.5.1(a) and P2.5.2(a), respectively.


Figure P2.5.1 MATLAB and PSpice simulations of a voltage doubler circuit (“voltage_doubler.opj”).




Figure P2.5.2 PSpice and MATLAB simulations of a voltage quadrupler circuit (“voltage_quadrupler.opj”).



Complete the above MATLAB script “voltage_doubler.m” to simulate the voltage doubler for 10s to get its input and output waveforms as shown in Figure P2.5.1(b). Also perform PSpice simulation of the circuit to get its input and output waveforms as shown in Figure P2.5.1(c).
Complete the following MATLAB script “voltage_quadrupler.m” to simulate the voltage quadrupler for 10 s to get its input and output waveforms as shown in Figure P2.5.2(b). Also perform PSpice simulation of the circuit to get its input and output waveforms as shown in Figure P2.5.2(c).




%voltage_quadrupler.m
clear
Is=2.682e-9; T=27; nVT=1.836*(273+T)/11605; % Diode constants
iDv = @(vD)Is*(exp(vD/nVT)-1);
dt=0.001; tf=10; ts=0:dt:tf; % Time vector
Vm=5; f=2; w=2*pi*f; vs=Vm*sin(w*ts); % Input source voltage
C1=1e-6; C2=1e-6; C3=1e-6; C4=1e-6;
vC1(1)=0; vC2(1)=0; vC3(1)=0; vC4(1)=0;
v2(1)=0; v3(1)=0; v4(1)=0; v5(1)=0;
for n=1:length(ts)
  vD1 = v?(n); iD1 = iDv(vD1);
  vD2 = v?(n)-v?(n); iD2 = iDv(vD2);
  vD3 = v?(n)-v?(n); iD3 = iDv(vD3);
  vD4 = v?(n)-v?(n); iD4 = iDv(vD4);
  vC1(n+1) = vC1(n) + (iD1?iD2?iD3?iD4)/C1*dt;
  vC2(n+1) = vC2(n) + (iD2?iD3?iD4)/C2*dt;
  vC3(n+1) = vC3(n) + (iD3?iD4)/C3*dt;
  vC4(n+1) = vC4(n) + iD?/C4*dt;
  v2(n+1) = vs(n) - vC?(n+1);
  v3(n+1) = -vC?(n+1);
  v4(n+1) = v2(n+1) - vC?(n+1);
  v5(n+1) = v3(n+1) - vC?(n+1);
end
plot(ts,vs, ts,v5(1:end-1),'r'), grid on






2.6 Half‐wave Rectifier Circuit Fed by a Triangular Voltage Source Consider the half‐wave rectifier circuit of Figure P2.6(a) where the voltage source v_i generates a triangular voltage waveform (with amplitude 10 V and frequency f = 1 kHz) shown in Figure P2.6(c).


Figure P2.6 Half‐wave rectifier circuit fed by a triangular voltage source.



 To get the upper/lower limit V_H/V_L of the output voltage v_o(t) and the rising/falling period T_R/T_F via an analytical approach using MATLAB, we set up the following equations like Eq. (2.2.3) referring to Figure P2.6(c):
(P2.6.1a) 
(P2.6.1b) 
(P2.6.1c) 
Noting that V_H is already known as V_H = V_m − V_TD = 5 − 0.65 = 4.35, we can solve this set of equations to find V_L = 3.94, T_R = 0.02 ms, and T_F = 0.98ms by saving these equations into an M‐file named, say, ‘elec02p06_f.m’ and running the following MATLAB script “elec02p06a.m.”




%elec02p06a.m
global Vm f VTD T D
Vm=5; f=1000; T=1/f; D=T/2; VTD=0.65;
VH=Vm-VTD; % Local maximum (High Voltage) of vo(t)
R=5e3; C=1e-6;
x_0=[0 0 0]; % Initial guess of [VL TR TF]
x=fsolve('elec02p06_f',x_0,optimset('fsolve'),C,R)
VL=x(1); TR=x(2); TF=x(3);
fprintf('\n VH=%8.4f, VL=%8.4f, TR=%8.4fms, TF=%8.4fms',
	                        VH,VL,TR*1000,TF*1000)
Vr=VH-VL, VH*T/R/C % Ripple Eq. (P2.6.2)
IC_avg=C*Vr/TR; % Eq. (P2.6.4)
Vo_avg=(VH?VL)/2 % Eq. (P2.6.5)
IR_avg=Vo_avg/R % Eq. (P2.6.6)
ID_avg=IC_avg?IR_avg % Eq. (P2.6.7)
function y=elec02p06_f(x,C,R)
global Vm f VTD
VH=Vm-VTD; w=2*pi*f; T=1/f; VL=x(1); TR=x(2); TF=x(3);
y=[VH*exp(-TF/R/C)-VL; VH-VL-4*Vm*TR/T; TR+TF-T]; % Eqs. (P2.6.1)






To simulate the half‐wave rectifier by using MATLAB, complete and run the following script “elec02p06b.m” (after “elec02p06a.m”) to get the simulation result as shown in Figure P2.6(c).


 


%elec02p06b.m
tf=2.5*T; dt=tf/5000; t=0:dt:tf; % Time range
% Input voltage
tri_wave_=@(t,D,T)mod(t,T)/D.*(mod(t,T)<D)+ ...
      (1-mod((t-D),T)/D).*(mod(t,T)>=D).*(mod(t,T)<2*D);
vi = 2*Vm*tri_wave_(t,D,T)-Vm; % Input voltage waveform
% Rectification
Is = 1e-14; % Saturation current
[vo,vD,iD,iR] = rectifier_RC([vi; t],R,?,Is);
plot(t,vi,'g', t,vo,'r', t,100*iD,'m', t([1 end]),[0 0],'k')
legend('v_i (t)','v_o (t)','100*i_D (t)')
N1=floor(T/dt); nn0=1:N1;
[VH,imin]=max(vo(nn0)); VH % Te 1st peak value of vo(t)
tH1=t(imin); % The 1st peak time
N2=2*N1+10; nn1=N1:N2;
[VL,imin]=min(abs(vo(nn1))); VL
tL1=t(N1-1+imin); % The 1st valley time
[emin,imin]=min(abs(vo(nn1)-VH));
tH2=t(N1-1+imin); % The 2nd peak time
TF=tL1?tH1 % Falling period
TR=tH?-tL1 % Rising period




Assuming that T_R ≪ T ≪ RC so that T_F = T – T_R ≈ T ≪ RC, show that the ripple voltage V_r = V_H – V_L is approximately
(P2.6.2) 
Noting that the capacitor voltage charged during the rising period T_R is equal to the ripple voltage V_r and is related with the capacitor current i_C or its average I_C,avg is as
(P2.6.3) 
find the average of the capacitor current through C:
(P2.6.4) 
Also, noting that the average of the output voltage (across R||C) is
(P2.6.5) 
find the average of the resistor current through R:
(2.80)
Also, find the average of the diode current through D:
(P2.6.7) 
To simulate the half‐wave rectifier by using PSpice, draw the schematic as Figure P2.6(b) and perform the Transient analysis for 2.5 ms to get the input and output voltages and diode current as shown in Figure P2.6(d). You can activate or deactivate two cross cursors by clicking on the toggle cursor button in the PSpice A/D (Probe) window and move them to any two points by left‐/right‐clicking or pressing the (left or right) arrow/shift‐arrow to read their coordinates simultaneously where you can left‐/right‐click on the symbol of the variable (below the waveforms) which you want to read.
Does the value of I_D,avg agree with the (approximate) average of the diode current i_D(t) (during the ON period) shown in Figure P2.6(c) or (d)?

2.7 Precision Full‐wave Rectifier
Consider the precision full‐wave rectifier in Figure P2.7(a) where the maximum (saturation) output voltage and maximum (short‐circuit) output current of the OP Amp μA741 are V_om = 14.6 V and I_os = 40 mA, respectively, for a bipolar power supply of ±15 V.

Noting that the OP Amp U1 has always a negative feedback path (via R₂) so that v_‐1 = v₊₁ by the virtual short principle, let us see how the rectifier works. If v_i > 0, v_o0 becomes (low, high) so that D₁ can be (off, on) and thus i_o0 = 0,  = 0, and v₋₁ = v₊₁ = v_i. Then  so that . If v_i < 0, v_o0 becomes (low, high) so that D₁ can be (off, on) to activate the negative feedback path for the OP Amp U2, resulting in  (virtual ground). Then the OP Amp U1 functions as an inverting amplifier with gain −R₂/R₁ so that .
Doesn't the value of R₃ seem to matter? To check your idea, resimulate the rectifier with R₃ = 100 Ω to get v_o(t), v_‐2(t), and 10i_D(t) as shown in Figure P2.7(c) where v_o(t) has been severely distorted in the middle of the negative cycle of v_i(t). Why is that? It is because v₋₁ = v₊₁ = v₋₂ ≠ v₊₂ = 0, i.e. the virtual short principle does not hold despite the negative feedback path via D₁ with i_D = i_o0 > 0. What caused this situation starting from just when v_i is about to decrease below −4 V so that − = i_o0 is going to increase over (v₊₁ − v_i)/R₃ = (v₋₂ − v_i)/R₃ = 40 mA = I_os? What is the minimum value of R₃ to avoid such a situation?



Figure P2.7 A precision full‐wave rectifier.


2.8 Precision Full‐wave Rectifier
Consider the precision full‐wave rectifier with the PSpice schematic shown in Figure P2.8(a) where R₁ = R₂ = R₃ = R₄ = R₅ = 1 kΩ and the maximum (saturation) output voltage of the OP Amp μA741 is V_om = 14.6 V for a bipolar power supply of ±15 V.

Noting that the OP Amp U1 as well as U2 has always a negative feedback path via R₂-D₁ (when v_i > 0) or via D₂-R₅ (when v_i < 0) so that v_‐1 = v₊₁ = 0 and v_‐2 = v₊₂ by the virtual short principle, let us see how the rectifier works. When v_i > 0, v_o0 becomes (low, high) so that D₁/D₂ can be (on/off, off/on) and thus ,  where both U1 and U2 work as linear amplifiers each with gain −R₂/R₁ and –R₄/R₃, respectively. Then
(P2.8.1) 
When v_i < 0, v_o0 becomes (low, high) so that D₁/D₂ can be (on/off, off/on). KCL at node 1 yields a node equation with v₃ as an unknown variable:
(P2.8.2) 



Figure P2.8 A precision full‐wave rectifier.


Then, regarding R₂-R₃-R₄ as a voltage divider, we can find the output voltage v_o as
(P2.8.3) 
Find the peak inverse voltages (PIVs) of the diodes D₁ and D₂.
When v_i = V_m = 5 V, v_o0 becomes low so that D₁ is on with  =  = 0.7 V and D₂ is reverse‐biased with

When v_i = −V_m = −5 V, v_o0 becomes high so that D₂ is on with  =  = 0.7 V and D₁ is reverse‐biased with
(P2.8.4) 
These PIVs can also be seen from the simulation result in Figure P2.8(b).


2.9 Zener (Shunt) Regulator
Consider the Zener regulator shown in Figure 2.20(a) where the Zener diode has V_Z = 6.8 V at I_Z = 5 mA, r_Z = 20 Ω, and I_ZK = 0.2 mA, and the supply voltage v_S varies by ±1 V around its nominal value 10 V.

Determine V_Z0 of the linear i_Z‐v_Z relation (2.3.1b) describing the almost‐straight line part of the i‐v characteristic curve of the Zener diode.
Substituting (I_Z, V_Z) = (5 mA, 6.8 V) and r_z = 20 Ω into Eq. (2.3.1b) yields
(P2.9.1) 
Use the equivalent circuit (Figure 2.20(b)) with the Zener diode Z replaced by its PWL model to find the output voltage v_o = v_Z (across R_L = 2 kΩ in parallel with the Zener diode) to the source voltage v_s = 10, 9, 8.3 V.
We can use Eq. (2.3.8) to get
(P2.9.2) 

>>([10 9 8.3]/500+6.7/20)/(1/500+1/20+1/2000)

However, for the third value v_Z = 6.697 V < V_Z0, we set i_Z = 0 (I_ZK) and use the voltage divider rule to redetermine v_Z as if there were no Zener diode branch:
(P2.9.3) 
Make use of Eq. (2.3.9a) to guess how v_Z (the voltage across the Zener diode or R_L = 2 kΩ) will be changed by the ±1V‐change in v_s.
(P2.9.4) 
You can run the following MATLAB statements to get a help in finding the answers to the above questions:

        >>VZ=6.8; IZ=5e-3; rz=20; IZK=0.2e-3;
          vss=[10 9 8.3]; Rs=500; RL=2e3;
 [vos,iZ,dvodvs,dvodRL,dvodIL,Rsmax,RLmin,VZ0]= ...
   Zener_regulator(VZ,IZ,rz,IZK,RL,Rs,vss)

Is your guess close to the real change in v_Z (across R_L = 2 kΩ to v_s = 10V) caused by the −1V‐change in v_s, which can be observed in Eq. (P2.9.2)?
Use the equivalent circuit (Figure 2.20(b)) to find the output voltage v_o = v_Z (across R_L = 2, 1.9, 1.4 kΩ in parallel with the Zener diode) to the source voltage v_s = 9 V.
We can use Eq. (2.3.8) to get
(P2.9.5) 

       >>(9/500+6.7/20)./(1/500+1/20+1./[2 1.9 1.4]/1e3)

However, for the third value v_Z = 6.696 V < V_Z0, we set i_Z = 0 (I_ZK) and use the voltage divider rule to redetermine v_Z as if there were no Zener diode branch:
(P2.9.6) 
Make use of Eq. (2.3.9b) to guess how v_Z (to v_s = 9 V) will be changed by the ±100 Ω‐change in R_L.
(P2.9.7) 
You can run the following MATLAB statements to get a help in finding the answers to the above questions:

>>vs=9; Rs=500; RLs=[2e3 1.9e3 1.4e3];
 [vos,iZ,dvodvs,dvodRL,dvodIL,Rsmax,RLmin,VZ0]=...
 Zener_regulator(VZ,IZ,rz,IZK,RLs,Rs,vs); vos, dvodRL

Is your guess close to the real change in v_Z (across R_L = 2 kΩ to v_s = 9V) caused by the −100 Ω‐change in R_L, which can be observed in Eq. (P2.9.5)?
To see that for v_s ≤ 8.3V, v_Z gets distinctly away from V_Z = 6.8V at R_L = 2 kΩ, perform a PSpice simulation by taking the following steps:

Draw the PSpice schematic including a DC voltage source Vdc (10V), a sinusoidal voltage source VSIN (with amplitude 2 V and frequency 1 Hz), a Zener diode DbreakZ, two resistors R_s = 500 Ω and R_L = 2 kΩ, and a Ground, as shown in Figure P2.9.1(a). If DbreakZ is not found in the Part List (Part Browser dialog box) when you type ‘DbreakZ’ in the Part text box of the Place Part dialog box (Figure P2.9.1(b)) opened by Place part button on the tool palette (Figure P2.9.1(a)), you should insert the BEAKOUT library into the Libraries list by clicking on the Add library button and selecting Cadence > … > tools > capture > library > pspice > breakout.olb.


Figure P2.9.1 PSpice simulation for the Zener regulator in Problem 2.9 (“voltage_regulator_zener0.opj”).



Select the symbol of DbreakZ by clicking on it, select ‘Edit > PSpice Model’ (from the menu bar) to open the PSpice Model Editor window, and type ‘BV = 6.8V IBV = 5mA’ to set V_Z = 6.8V and I_Z = 5 mA (Figure P2.9.1(c)).
Set the Analysis type, Run to time, and Maximum step size as ‘Time Domain (Transient)’, 2 s, and 1 ms, respectively, in the Simulation Settings dialog box opened by clicking on the 
New/Edit Simulation Profile button from the toolbar (Figure P2.9.1(d)).
Place the voltage markers at the upper terminals of the voltage source Vs and resistor RL as shown in Figure P2.9.1(a).
Click 
Run to start the simulation and get the input/output voltage waveforms as shown in Figure P2.9.2.



Figure P2.9.2 PSpice simulation results for Problem 2.9.


Does the output voltage v_Z drop conspicuously below V_Z = 6.8V as the source voltage v_s becomes lower than 8.3V? How can the value of v_Z to the input source voltage v_s = 8V be estimated?