© Springer Nature Switzerland AG 2020

K. Y. ChengIII–V Compound Semiconductors and DevicesGraduate Texts in Physicshttps://doi.org/10.1007/978-3-030-51903-2_9

9. Heterostructure Electronic Devices

Keh Yung Cheng^{1, 2}  

(1)

Department of Electrical and Computer Engineering, University of Illinois at Urbana-Champaign, Urbana, Illinois, USA

(2)

Department of Electrical Engineering, National Tsing Hua University, Hsinchu, Taiwan

 

 

Keh Yung Cheng

Email: kycheng@ee.nthu.edu.tw

Abstract

Compound semiconductors are excellent candidates for high-speed device applications due to their high electron mobility, the ability to form heterostructures, and the availability of semi-insulating substrates. However, the multicomponent nature and the lack of robust native oxides make the fabrication of compound semiconductor-based metal-oxide-semiconductor field-effect transistors (MOSFETs) an extremely difficult task. Instead, GaAs-based metal–semiconductor field-effect transistors (MESFET) were developed initially. A MESFET utilizes a metal–semiconductor Schottky barrier to replace the MOS gate structure. The charge carriers in the active region (channel) are separated spatially from the control (gate) electrode by a depletion layer formed on the semiconductor surface. Nevertheless, due to the nature of the Schottky barrier and high electron mobility, only n-channel MESFETs were studied and the devices are leaky at high positive biases. With the advancements of epitaxial growth technology and new device concepts, efficient advanced devices were developed. Among many three-terminal device structures, the modulation-doped field-effect transistor (MODFET), or high-electron-mobility transistor (HEMT), and the heterojunction bipolar transistor (HBT) are the most widely used high-speed devices. In this chapter, after a brief review of the MESFET, the development and working principles of HEMTs and HBTs are discussed in great detail. Then the key concepts of achieving an oxide-semiconductor interface with low interface state density necessary for the fabrication of high performance III–V MOSFETs are discussed.

The HEMT is a voltage-controlled majority carrier device. It shares the same device geometry as the MESFET except for the details of the active region. The control electrode (gate) is coupled to the active region of the device through a capacitor. The conduction carriers, in the form of the two-dimensional electron gas (2DEG), in the active region are generated by modulation doping at the heterostructure interface.

The structure of the HBT is similar to that of the homostructure bipolar junction transistor (BJT), with the emitter–base junction replaced by a heterojunction. With properly designed heterojunctions, the device parameters such as doping level and layer thickness can be individually optimized for high-speed and high-gain operations. The HBT is a current-controlled minority carrier device with the charged carriers being separated energetically by the energy barriers. The control electrode (base) is resistively coupled to the active device region. The major device attributes of FETs and BJTs are compared in Table 9.1.

Table 9.1

Comparison of BJT and FET

	Carriers	Transport	Output control	Input impedance
BJT	Minority	Diffusion	Base current	Low
FET	Majority	Drift	Gate voltage	High

In late 1990, the inversion-mode GaAs MOSFET with a low interface trap density was finally achieved using in situ electron beam evaporated Ga₂O₃(Gd₂O₃) dielectric film on MBE GaAs. Next, using ex situ atomic layer deposited high-κ Al₂O₃ and HfO₂ films as the gate dielectric, similar devices were demonstrated on GaAs and other III–V materials. Further refinement of oxide deposition methods and development of additional high-κ gate dielectrics were exploited in the following two decades. At the moment, III–V MOSFET manufacturing technologies are still under development.

9.1 Metal–Semiconductor Field-Effect Transistors (MESFETs)

9.1.1 Basic Operation Principles

As a prelude to the HEMT, the device characteristics of the MESFET are discussed first. The operating principle of the MESFET is identical to that of a junction FET, and its structure is also similar except that the p–n junction is replaced by the Schottky barrier. Most MESFETs use n-type III–V compound semiconductors for the conduction channel because of their high electron mobility and large Schottky barrier height. To minimize the parasitic capacitance, semi-insulating substrates are usually used. A schematic diagram of the MESFET is shown in Fig. 9.1. The active region of the device has a conduction channel thickness a, a gate length L, and a gate width Z. The depletion region has a non-uniform thickness of W(x) along the channel under a large drain bias voltage.

Fig. 9.1

Schematic structure and dimension of a metal–semiconductor FET. The shaded region is the depletion region under the gate electrode

Under normal operation, the source is grounded, the gate is reverse-biased to modulate the conduction channel, and the drain contact is biased at a proper voltage to collect majority carriers. The effect of the applied drain voltage, V_D, with the gate open, on the current–voltage relationship is investigated first. When a small positive V_D is applied with V_GS = 0, the channel of the MESFET is essentially a uniform resistor with a cross-sectional area determined by the width of the device (Z) and the non-depleted channel thickness (a − W). The channel current I_D is a linear function of the drain voltage as shown in Fig. 9.2. The depletion width along the conduction channel has a constant value of

Fig. 9.2

General form of the current–voltage characteristics of a MESFET. The pinch-off point defines the saturation drain voltage, V_D(sat)

(9.1)

where V₀ is the contact potential of the Schottky barrier gate, N_d is the carrier concentration of the channel, and is the permittivity of the semiconductor.

When a moderate V_D of a few tenths of a volt is applied with V_GS = 0, the V_D simultaneously reverse biases the gate–drain metal–semiconductor junction and widens the depletion region near the drain contact. The depletion region width increases along the conduction channel from source to drain. The depletion width closest to the drain contact becomes

(9.2)

The narrowing of the conduction channel leads to an increased channel resistance. The increasing of channel current I_D deviates from the linear relationship with increasing V_D. Continuing to increase V_D causes an ever-increasing depletion of the channel. Eventually, the conduction channel vanishes near the drain contact, where the depletion width approaches the channel width for V_GS = 0.

(9.3)

The drain voltage V_D becomes the saturation drain voltage V_D(sat) and can be represented as

(9.4)

At the saturation voltage and beyond, the drain current becomes saturated, I_D(sat) and does not increase with V_D.

Next, we will investigate the gate bias effect. When the gate-to-channel junction of a MESFET is reverse-biased, the depletion width gets wider, and V_D(sat) will decrease.

(9.5)

Since V_GS is negative for reverse bias of the gate–channel junction, V_D(sat) is decreased as shown in Fig. 9.3.

Fig. 9.3

Modification of current–voltage characteristics for V_G < 0

The depletion width W eventually will reach across the channel thickness a when the gate reverse bias is further increased. The gate voltage at which the conduction channel is pinched off when V_D = 0 is called the threshold voltage V_T. For a gate bias of V_GS and V_D = 0, the depletion width is expressed as

(9.6)

At the threshold voltage V_GS = V_T, W = a. This leads to

(9.7)

(9.8)

We define V_P as the pinch-off voltage, which is the potential across the depletion region at the threshold condition (W = a).

(9.9)

The depletion width in a MESFET with V_GS = 0 can be either greater than or less than the channel thickness because of the contact potential. If W < a, a channel exists with zero gate bias. The device is operated in the depletion mode. On the other hand, if W > a, the depletion region extends across the channel in equilibrium, and no significant channel current can flow. A positive gate voltage must be applied to reduce the depletion width to a value smaller than the channel thickness a. The device is operated in the enhancement mode.

Figure 9.4 shows the energy band diagrams of a depletion-mode MESFET under V_D = 0 and various V_GS. A reverse bias on the gate (V_GS < 0) is required to modulate the channel width. The threshold voltage V_T can also be termed the ‘turn-off’ voltage of the device. For enhancement-mode MESFETs, a positive gate bias is required to open the channel. The energy band diagrams for various bias conditions (V_D = 0) are shown in Fig. 9.5.

Fig. 9.4

Depletion region profile under the gate and energy band diagrams of depletion-mode MESFET under V_D = 0 and various V_GS (negative)

Fig. 9.5

Depletion region profile under the gate and energy band diagrams of enhancement-mode MESFET under V_D = 0 and various V_GS (positive)

9.1.2 Current–Voltage Characteristics

A one-dimensional model is used to develop the DC current–voltage (I–V) characteristics of a MESFET. It is assumed that no breakdown will be induced before the channel is pinched off and the device has a doping density of N_d in the channel. Furthermore, the active region of the MESFET has a channel length L, junction width Z, channel depth a, depletion width W(x), and conducting channel width h(x). The origin of the x-axis is located at the edge of the gate adjacent to the source. A schematic of the MESFET structure and the corresponding voltage drop due to the drain bias is shown in Fig. 9.6.

Fig. 9.6

Schematic diagram of the conducting channel, dimensions, and potential drop along the channel

The current at position x in the channel is described as

(9.10)

where σ is the channel conductivity, ρ is the resistivity of the channel material, , and . Since the drain current is a constant and independent of x, we can solve I_D by integration.

(9.11)

where G₀ is the channel conductance at W(x) = 0 and G₀ ≡ Za/ρL. This is the complete I–V characteristic equation for all bias conditions.

In the low bias region, where V_D ≪ V₀ − V_GS, the I–V characteristics have a linear relationship. We can first rewrite I_D in the following form:

(9.12)

Then, using Taylor series expansion of for x ≪1, we have

(9.13)

The drain current simply increases linearly with drain bias voltage.

At the other end of the spectrum, the conduction current saturates at high drain bias when the channel is pinched off. The I–V relationship described above is only valid up to pinch-off, where . Using this pinch-off voltage relation in (9.11), the saturation current is obtained as

(9.14)

This equation can be further reduced by replacing with .

(9.15)

The typical I–V characteristics of an n-channel depletion-mode MESFET are shown in Fig. 9.7. The drain current flows for V_GS are less negative than the threshold voltage V_T. At sufficiently high drain bias, V_B, avalanche breakdown occurs between the gate and drain and the drain current increases abruptly.

Fig. 9.7

Typical current–voltage characteristics of a depletion-mode MESFET. Breakdowns occur at the breakdown voltages V_B

9.1.3 Transconductance and Equivalent Circuit of MESFET

One of the figures of merit of the MESFET is the transconductance, g_m, which describes the effect of the input voltage change on the output current. In the equivalent circuit model, the intrinsic transconductance g_mi times the input voltage represents a current source. Under a fixed drain bias, the change in gate voltage leads to a depletion layer width change. Because the space charge in the depletion region changes by ΔQ_G in a time interval of τ, a drain current change is induced.

(9.16)

The rate of conduction current change with respect to the charge change in the depletion region defines a carrier transient time (τ) crossing the conduction channel. The intrinsic transconductance, g_mi, is then defined as

(9.17)

C_G is the total gate capacitance and C_G = C_GS + C_DG, where C_GS and C_DG are the gate-to-source capacitance and drain-to-gate capacitance, respectively. To increase g_mi, we have to reduce τ. The minimization of τ can be achieved either by using materials with high drift velocity or by minimizing the channel length through the reduction of gate length. The approach of increasing the total gate capacitance to achieve high g_mi is not practical, since it will limit the frequency response of the device.

Next, we examine the property of the drain terminal. For a fixed gate bias, a change in V_DS will also change the space charge in the depletion region, ΔQ_G, which defines a current change, ΔI_DS, and leads to a drain-to-gate capacitance C_DG.

(9.18)

The current–voltage change further defines a drain-to-source output conductance (G_o):

(9.19)

where Q is the total charge in conduction channel.

Assuming the carrier velocity υ is constant in the conduction channel of an effective length L_eff, ΔI_DS ~ ΔQ/Δt, and Δt ~ L_eff/υ, the right-hand side of the output conductance (9.19) can be expressed as

(9.20)

C_o defines an output capacitance.

(9.21)

To achieve large G_o, high carrier mobility and small gate length are necessary.

Figure 9.8 shows a simple intrinsic equivalent circuit model of the MESFET that ignores all parasitic elements except the terminal series resistances R_G, R_S, and R_D.

Fig. 9.8

Intrinsic equivalent circuit model of the MESFET including terminal series resistances

9.1.4 High-Speed Figure of Merit

The high-frequency performance of a MESFET is usually characterized by parameters related to its ultimate operation frequency. However, these parameters are difficult to measure due to the fact that the performance of the device under testing can depend as much on the measurement circuit as on the device itself. As a result, high-frequency transistors are commonly characterized by frequency-dependent gains, deduced from network-analyzer measurements. The high-frequency performance of the device measured in this way is reasonably independent of the circuit in which it is placed. There are two gains commonly used to deduce the small signal, linear-operation figure of merit of the device. One of these gains is h₂₁, which is the forward current gain with the output short-circuited. The frequency at which this gain extrapolates to one is the unity short-circuit current gain frequency f_T. Consider the simple intrinsic equivalent circuit of Fig. 9.9. This frequency can be derived as the frequency at which the magnitude of the input current I_i equals the magnitude of the ideal output current g_miV_C of the transistor. When the output is short-circuited,

Fig. 9.9

Intrinsic equivalent circuit of a MESFET for frequency response analysis

(9.22)

(9.23)

This equation shows that f_T is a measure of a quantity that is fundamental to the device—the delay time of the current through the conduction channel.

The other important figure of merit of the transistor is the maximum frequency of oscillation, f_max. At this frequency, the unilateral power gain (U) of the device becomes unity. It is the highest frequency at which the transistor can amplify the power of a signal and can be expressed as

(9.24)

The f_max of a MESFET may be either above or below its f_T, depending on the specific circuit values in the above equation.

9.1.5 MESFET Fabrication and Performance

A typical fabrication sequence for a high-speed MESFET is shown in Fig. 9.10. The process was designed to maximize the cutoff frequency of the transistor by minimizing the contact resistances, reducing the parasitic in the active conduction channel, and shortening the gate length. An n⁺ contact layer is added on top of the conduction channel layer outside the gate region to reduce the source and drain contact resistances R_S and R_D. In addition, a thick channel layer outside the gate area is used to minimize the surface depletion-induced additional resistance. To maintain a short gate length while minimizing the gate contact resistance R_G, the usual practice is to use a ‘T’ gate design where a thick top metal contact with a narrow base is adopted. The gate is situated in a recess of the channel layer in order to control the threshold voltage, V_T. The gate recess is usually off-centered and located near the source contact to minimize R_S. The gate–drain separation, L_GD, is designed to be greater than the depletion width at the breakdown voltage.

Fig. 9.10

Typical fabrication sequence of submicron GaAs MESFET using the double-recess process. a Epitaxy and using photoresist (PR) to define device active area, b mesa etch for isolation, c source and drain ohmic contacts deposition, d channel recess etch and gate recess etch using bilayer PR process, e T-gate metal deposition, and f PR liftoff to complete MESFET process

The fabricated MESFETs are characterized by measuring their I–V characteristics, g_m, f_T, and f_max. Figure 9.11 shows the I–V characteristics of a 0.12 × 50 µm² dual-gate GaAs depletion-mode MESFET. The drain currents show weak saturation for the negative gate bias voltages. This is a common behavior called short-channel effect in MESFETs with gate length less than 0.25 µm.

Fig. 9.11

Measured I_D-V_DS characteristics and channel current and transconductance versus gate bias of a dual-gate (0.12 µm × 50 µm) GaAs MESFET.

Courtesy M. Feng, University of Illinois at Urbana-Champaign

The short-channel effect is due to the less efficient inter-valley transfer of electrons from the Γ-valley to the L-valley at high fields in short-channel devices. Thus, most electrons stay in the Γ-valley when reaching the drain and show as a weaker velocity saturation. The parasitic leakage through the semi-insulating substrate also contributes to the lack of current saturation for the more negative gate-voltage region. The transconductance g_m is deduced from the drain current variation under various gate bias voltages. Note that the measured g_m is the extrinsic transconductance including the effect of R_S and expressed as

(9.25)

The maxima f_T and f_max of the MESFET are estimated to be 110 and 235 GHz, respectively, and shown in Fig. 9.12. These values are deduced from the measured low-frequency values of h₂₁ and U_max up to 40 GHz using a roll-off of −6 dB/octave.

Fig. 9.12

Measured unity current gain frequency f_T (H₂₁) and maximum cutoff frequency f_max of the same dual-gate (0.12 µm × 50 µm) GaAs MESFET characterized in Fig. 9.11.

Courtesy M. Feng, University of Illinois at Urbana-Champaign

9.2 Modulation Doping and Two-Dimensional Electron Gas (2DEG)

As shown in Fig. 4.​7, the carrier mobility of a semiconductor is determined by the sum of inverse mobility components (µ_i) due to different scattering mechanisms, i.e., µ⁻¹ = Σ(µ_i)⁻¹. At a fixed temperature, the lowest mobility component dominates the total carrier mobility. In binary compound semiconductor alloys, the major scattering processes are the optical phonon (polar) scattering at high temperature, the ionized impurity scattering at low temperature, the acoustic phonon scattering due to piezoelectric field, and the acoustic phonon scattering due to deformation potential. With the exception of the impurity scattering, the effect of all scattering mechanisms on electron mobility can be reduced at low temperatures. The total temperature-dependent electron mobility increases with decreasing temperature and reaches a maximum value before decreasing with further reducing temperature. One way to reduce the ionized impurity scattering at low temperature is to use high-purity materials, as evidenced in Fig. 4.​7, where there are fewer ionized impurities. However, for most high-speed device applications, certain doping concentrations have to be maintained. Therefore, this option is not practical. In 1978, R. Dingle and colleagues at Bell Laboratories invented a modulation-doping technique to eliminate the influence of ionized impurity scattering in heterojunction superlattices [1]. By separating the physical location of ionized dopants from generated electrons across the heterojunction, with ionized impurities on the large bandgap semiconductor side and generated conduction electrons on the undoped small bandgap semiconductor side, electron mobility much higher than the equivalent bulk material was achieved at low temperature without sacrificing the carrier concentration. Since these conduction electrons occupy a thin layer (≤100 Å) in the triangular quantum well formed at the heterojunction interface, they can only move easily close to and parallel to the heterojunction interface. These electrons form an electron cloud, or a pseudo-two-dimensional electron gas (2DEG), in the modulation-doped heterostructure. Based on this concept, a new type of FET, the high-electron-mobility transistor (HEMT), was derived.

9.2.1 Modulation-Doped (MD) Heterostructures

The modulation-doping concept was first developed utilizing heterojunction superlattices as shown in Fig. 9.13. In a superlattice structure with type-I band alignment, quantum wells are formed in both conduction and valence bands. Under equilibrium conditions, a continuous Fermi level throughout the superlattice causes appreciable band bending, leading to the formation of pseudotriangular quantum wells at heterojunctions. When the superlattice is either uniformly doped (UD) or modulation-doped (MD) with donor impurities, due to the high potential energy associated with the barrier layer relative to the quantum well, electrons associated with donor impurities in barriers will move into quantum wells. In both UD and MD superlattice structures, the carriers confined to the pseudotriangular quantum well form a 2DEG. The ionized impurity scattering in the conduction channel is removed in MD structures, where 2DEG conduction electrons and their parent donor impurities are spatially separated from each other in an irreversible manner. The electron mobility of the 2DEG suffers no ionized impurity scattering, leading to a much higher mobility, especially at low temperatures. Figure 9.14 shows the temperature-dependent electron mobility of bulk, UD and MD GaAs structures. The UD and MD structures used the AlGaAs/GaAs material system. The electron mobility enhancement at low temperatures clearly demonstrates the reduction (or even a lack) of impurity scattering as expected. Since the doped barrier layers are totally depleted in MD superlattice structures, the electron density in the quantum well may greatly exceed the unintentionally doped impurity density. Thus, the concentration of 2DEG is independent of the doping level in the conduction channel. By the same token, an enhanced hole mobility of the two-dimensional hole gas (2DHG) is achievable in p-type MD heterostructures.

Fig. 9.13

Energy band diagrams for n-doped and undoped GaAs-Al_xGa_1−xAs superlattices.

Reprinted with permission from [1], copyright AIP Publishing

Fig. 9.14

Temperature-dependent electron mobility for bulk GaAs and several undoped UD and MD superlattices. The cross-hatched region includes most of the MD data.

Reprinted with permission from [1], copyright AIP Publishing

Of course, a superlattice heterostructure with multiple MD heterojunctions is not necessary for device implementation. With a proper energy band discontinuity, a single MD heterojunction is sufficient to form a 2DEG at the heterostructure interface and to achieve the electron mobility enhancement. In fact, for FET applications, the single MD heterojunction design makes it easy to control the channel charge carriers. The first FET utilizing the high-electron-mobility feature of the MD heterostructure has just one hetero-interface as shown in Fig. 9.15. This design first demonstrated by engineers at Fujitsu Laboratories in Japan—a high-electron-mobility transistor (HEMT) design, as it was called—became the standard structure of future FETs utilizing 2DEG in the conduction channel [2].

Fig. 9.15

Layer structure and energy band diagram of an MD GaAs-Al_xGa_1−xAs heterostructure grown by MBE with a spacer layer inserted between the barrier layer and the 2DEG channel.

Reprinted with permission from [2, 3], copyright Japanese Society of Physics

9.2.2 Scattering Mechanisms in MD Heterostructures

It is important to analyze various scattering mechanisms limiting the mobility in the 2DEG in order to be able to provide interface design rules for yielding high-performance devices. In addition to the bulk scattering mechanisms, some additional scattering mechanisms unique to heterojunctions are introduced here. A GaAs/AlGaAs MD heterostructure similar to the HEMT structure shown in Fig. 9.15 is used to illustrate the properties of added scattering mechanisms. On the semi-insulating GaAs substrate, an undoped GaAs channel layer was first grown, followed by a silicon-doped n-type AlGaAs barrier layer to complete the MD heterostructure. The 2DEG channel will be formed at the GaAs/AlGaAs interface just inside the undoped GaAs layer.

1. (a)

   Coulomb interaction from ionized impurities located in the barrier

    

Since the 2DEG is located right next to the hetero-interface, the physical quality of the interface as well as any force exerted that diverts the transport direction toward the interface will affect the nature of carrier scattering. The attraction force due to Coulomb interaction between 2DEG in the conduction channel and its ionized parent donor impurities in the barrier layer will cause electrons to scatter with the hetero-interface. The electron mobility is reduced due to this added scattering mechanism. The carrier mobility is thus a function of the 2DEG sheet charge density. At a low barrier doping density (small 2DEG sheet charge density), the Coulomb interaction is weak and the electron mobility is limited by the background scattering in the undoped GaAs channel. For a heavily doped barrier layer structure, the Coulomb interaction dominates the carrier scattering process.

The Coulomb scattering problem cannot be totally eliminated but can be reduced by setting back the doping region of the barrier layer away from the hetero-interface. This undoped barrier layer inserted between the 2DEG and doped barrier layer is called a spacer layer [4]. Remember, the Coulomb attraction force is inversely proportional to the square of the charge separation distance. For a fixed doping density in the barrier, the Coulomb interaction between the 2DEG and ionized donors weakens with increasing spacer layer thickness, thus increasing electron mobility. However, due to the decreased electron transfer rate from the thicker barrier layer to the conduction channel, for a fixed barrier doping density, the sheet density of the 2DEG will decrease with increasing spacer layer thickness. In practical devices, a compromised spacer layer thickness of 25–30 Å is used to optimize the electron mobility while maintaining a high 2DEG sheet charge density.

1. (b)

   Interface-roughness-induced scattering

    

Since the 2DEG in the conduction channel of an MD heterostructure is located very close to the hetero-interface, any minute interface roughness could induce additional scattering and decrease the carrier mobility. Normally, in MD heterostructures, the AlGaAs barrier layer is grown on top of the GaAs 2DEG channel layer using MBE. The surface morphology of the GaAs channel layer at the hetero-interface is critically important. An extremely flat and smooth GaAs/AlGaAs interface is usually achieved under proper growth conditions including a wide range of V/III flux ratio, substrate temperature, and growth rate. This layer structure is convenient for FET-like device fabrication, including HEMT, and is called the normal MD heterostructure. If the layer sequence is reversed such that the GaAs 2DEG channel layer is placed on top of the AlGaAs barrier layer, the structure is called an inverted MD heterostructure. To achieve high electron mobility in such structures, an extremely smooth AlGaAs surface morphology is required. However, only under a very narrow MBE growth window does the AlGaAs show a less rough surface. Figure 9.16 shows the difference in the 77 K electron mobility for normal and inverted MD heterostructures grown at various substrate temperatures with a 75 Å spacer layer. The 2DEG mobilities for normal and inverted MD structures are shown at different scales in the figure. Note that, even using the optimal AlGaAs growth temperature, the electron mobility of the inverted structure is still an order of magnitude smaller than that of the normal structure.

Fig. 9.16

Measured 2DEG mobility of normal and inverted MD GaAs/AlGaAs heterostructures grown at different temperatures.

Reprinted with permission from [4], copyright AIP Publishing

1. (c)

   Inter-subband scattering at high carrier density

    

Since the 2DEG is confined in the quasi-triangular QW at the hetero-interface, electrons are occupying the quantized states of the QW. The ground state gets populated first with electrons transferred from the barrier layer. When the ground state is fully populated, any further increase of the transferred electron density will have to occupy the higher energy states. The scattering probability is increased for the multiple-state system, and it reduces the total electron mobility.

The electron mobility values of the modulation-doped heterostructures have progressed steadily since 1978 (Fig. 9.17). In just three years, low-temperature electron mobility of over one million (cm²/V s) was achieved in many laboratories. Further improvements of MD heterostructure designs and growth techniques pushed the electron mobility of the 2DEG over the 10 million (cm²/V s) mark in 1989 at Bell Laboratories. A very thick spacer layer (70 Å) and planar (delta) doping scheme were used to minimize the Coulomb-interaction-induced interface scattering. The superlattice buffer layer beneath the GaAs channel was extensively used to guarantee minimized interface roughness scattering. Furthermore, to minimize the background doping concentration in the GaAs channel layer, the MBE system was thoroughly baked at high temperature (>200 °C) to get rid of volatile impurities inside and kept under liquid nitrogen cooling all the time. These grown samples provided a wonderful playground for some solid-state physicists, but have no immediate device application due to the low 2DEG sheet charge density achieved.

Fig. 9.17

Progress of peak mobility achieved in 2DEG as a function of temperature over a span of 12 years

Reprinted with permission from [5], copyright AIP Publishing

9.3 High-Electron-Mobility Transistor Basics—A Triangular Quantum Well Approach

The FET structure based on a 2DEG in the conduction channel was first demonstrated in 1980 by Fujitsu Laboratory of Japan, less than two years after the inception of the MD concept at Bell Laboratories. Therefore, there were different names used for this newly developed FET. The Fujitsu group called it the HEMT (high-electron-mobility transistor), Bell Laboratories named it SDHT (selectively-doped hetero-field-effect transistor), and the group at Thomson CSF in France called it TEGFET (two-dimensional electron gas field-effect transistor). The name MODFET (modulation-doped field-effect transistor) has also been used. Today, HEMT is the most commonly used name for this kind of FET.

The basic device structure of the HEMT is very similar to a MESFET, as shown in Fig. 9.18. Similar to a MESFET, the conduction current flows between the source and drain, and the amount of current flow is controlled by the gate bias. However, a HEMT does not use the gate bias to adjust the width of the conduction channel. Rather, the gate bias modulates the Fermi level position and, thus, controls the 2DEG sheet carrier density in the conduction channel. In this section, we will use a simple pseudotriangular QW approach to examine the equilibrium 2DEG sheet carrier density of a heterostructure.

Fig. 9.18

Schematic structure of a GaAs/AlGaAs high-electron-mobility transistor

An ideal triangular QW structure has an infinitely high vertical barrier on one side and a constant slope on the other side. The eigenenergy solutions of the ideal triangular QW are in the form of the Airy functions. If an ideal triangular QW was assumed for the HEMT structure, electrons transferred from the barrier layer fill the first allowed state (E₀) in the QW up to the Fermi level (E_F). Under ideal conditions, carriers of the 2DEG are solely transferred from the doped barrier layer with a doping concentration N_d and a depletion layer thickness W_d. Thus, the sheet carrier concentration of the 2DEG, N_S, simply equals to N_dW_d (cm⁻²). However, one should notice that the conduction band structure of the HEMT is far from ideal—the pseudotriangular QW has a finite band discontinuity, ΔE_c, on one side and a sublinear energy barrier on the channel side as shown in Fig. 9.19 for an AlGaAs/GaAs HEMT.

Fig. 9.19

Heterojunction energy band diagram of the HEMT structure shown in Fig. 9.18. The spacer layer in AlGaAs is removed from the heterojunction interface

Using an ideal triangular QW model, the possible sheet charge density (N_S) is estimated first. From Gauss’ law for an ideal triangular QW, the displacement flux density (D) relates the sheet charge density and the electric field intensity (F) by

(9.26)

Therefore, the ground state inside the QW, E₀, can be expressed in terms of N_S by

(9.27)

At T = 0 K, where f(E) = 1, the equilibrium sheet carrier density is given by

(9.28)

At a finite temperature,

(9.29)

If we include a thin undoped spacer layer with a thickness of W_sp at the interface, a voltage drop V_sp will appear across this layer. According to the energy band diagram shown in Fig. 9.20, the conduction band discontinuity ΔE_c at 0 K can be expressed as the following:

Fig. 9.20

Heterojunction energy band diagram of the HEMT structure shown in Fig. 9.18. The spacer layer in AlGaAs at the heterojunction interface is included

(9.30)

where

(9.31)

Here the bottom tip of the triangular QW is set as E = 0. We notice that each term, except E_d, in this equation is a function of N_S and has a unique solution for each E_F. By moving the E_d term to the left of the equation, the right-hand side of the equation can be expressed in terms of N_S.

(9.32)

(9.33)

Assuming an Airy function for the ideal triangular QW and using the appropriate material parameters, one can solve N_S self-consistently.

However, the difficulty in solving N_S from the above equation lies in the determination of the eigenenergy E₀, since E₀ depends on the shape of the potential well. In a realistic quasi-triangular QW, E₀ cannot be determined exactly. Therefore, instead of solving N_S rigorously, one can qualitatively understand the factors that control N_S using the following extreme conditions. Assuming the density of states of the ground state subband is so large that the Fermi level is close to the bottom of the well, E_F ≈ 0. For a very small spacer layer, W_sp ≈ 0, the charges in the AlGaAs barrier are totally depleted by the conduction band discontinuity and transferred to the QW, forming a 2DEG.

(9.34)

For a thick spacer layer, , the transferred N_S is small and we can neglect the term contains .

(9.35)

For a GaAs/AlGaAs HEMT with N_d = 10¹⁸ cm⁻³, ΔE_c = 0.2 eV, and , the sheet electron concentrations under these two extreme conditions are calculated as

(9.36)

These numbers are ~30% overestimated: In the first case, for W_sp = 0, E_F ≠ 0 and requires a lot more electrons to fill the subband. In the second case, due to the large extent of the spacer layer, only a portion of the doped barrier is depleted. Even at these overestimated values, they are still much smaller than that of a comparable GaAs MESFET with a 0.2 µm conduction channel doped to 10¹⁷ cm⁻³ (2–3×10¹² cm⁻²). Since a large N_S can reduce the channel resistance and increase current drive capability of the FET, a large N_S is desirable for device applications. Therefore, it is critical to maximize the carrier density of the HEMT. Empirically, N_S is proportional to N_dΔE_c/W_sp in a HEMT. Based on this relation, we should select material systems with a large ΔE_c, a small W_sp, and a maximum N_d.

9.4 Operation Properties of the HEMT

The operation of the HEMT can be best understood through the analysis of its energy band diagram. Unlike MESFETs, the sheet charge density in a HEMT is controlled by the Fermi level position relative to the QW subbands shown in Fig. 9.21. The Fermi level position in the quasi-triangular QW is determined by the work function of the gate metal, barrier layer thickness, doping concentration, conduction band discontinuity, and gate bias. In a properly designed HEMT, through the modulation of the Fermi level, the gate bias voltage V_GS directly controls the sheet charge density similar to that of MESFETs. Depending on the device parameters, depletion-mode and enhancement-mode operations of HEMTs are also expected.

Fig. 9.21

Conduction band diagram of a depletion-mode HEMT under a gate bias of V_GS < 0. The work function of the metal contact, qϕ_m, is also shown

9.4.1 Isolated Heterojunction Under Equilibrium

To understand the relationship between the applied gate bias and the Fermi level position or sheet charge density, we first examine the 2DEG heterojunction under equilibrium conditions. In the band diagram shown in Fig. 9.22a, the undoped conduction channel layer and the n-type-doped barrier layer are assigned as regions 1 and 2, respectively. The origin of this 1D diagram is set at the hetero-interface with a depletion width of W_d into the infinite long barrier layer. We also assumed an undoped spacer layer of W_sp on the barrier layer side of the heterojunction, a dopant ionization energy of E_d and a potential barrier height of qV_b0 formed by the depletion layer at the hetero-interface.

Fig. 9.22

a Energy band diagram in conduction band, b charge distribution, and c electric field distribution at the heterojunction of a HEMT

Under equilibrium, according to Gauss’ law, at the hetero-interface, it follows that

(9.37)

(9.38)

(9.39)

where D, F, and are the displacement flux density, electric field intensity, and permittivity, respectively. In this section, all discussions concern material 2 only; we will use instead of for simplicity.

Assuming donors in the barrier layer are fully ionized between −W_d ≤ z ≤ –W_sp and remain neutral beyond −W_d, Poisson’s equation can be written as

(9.40)

And, as shown in Fig. 9.22b, the charge distribution is

(9.41)

Thus, in the depletion region of the doped barrier

(9.42)

Using the boundary condition of F = 0 at z = –W_d, we found (Fig. 9.22c)

(9.43)

In the spacer layer, F is a constant of

(9.44)

The electric field intensity distribution across the depletion region of the heterojunction is shown in Fig. 9.22c.

The electric field intensity in the barrier has a slope of . The potential drop across the doped barrier layer (layer thickness ≫ W_d) can then be calculated as

(9.45)

By the same token, the potential drop across the spacer layer becomes

(9.46)

The total potential drop across the barrier is the sum of V_b0 and V_sp.

(9.47)

9.4.2 Charge Control by Gate Bias in HEMT

In HEMT structures, the doped barrier layer has a finite thickness and a metal Schottky gate is applied on the surface. The Schottky barrier also creates a surface depletion layer. It substantially alters the conduction band shape of the barrier layer and plays an important role in determining the Fermi level position. To simplify the discussion, assume the doped barrier layer is completely depleted. Relative to the surface, as shown in Fig. 9.23, the potential drop across the barrier is defined as V_i.

Fig. 9.23

Energy band model of a HEMT under a gate bias V_GS < 0. In this model, it is assumed that, under all bias conditions, the barrier layer beneath the gate is completely depleted

(9.48)

This potential difference V_i can also be derived from Poisson’s equation.

(9.49)

and

(9.50)

Thus, the electric field intensities in the depleted doped barrier and spacer layers are

(9.51)

Assuming .

The potential drop across the depleted barrier layer can then be calculated as

(9.52)

(9.53)

The potential drop across the spacer layer is simply F′W_sp. Letting V(0) = 0, the potential drop V_i can be expressed as

(9.54)

Here we defined a pinch-off voltage of just like a MESFET. Since , we can write the sheet charge density in (9.54) as a function of voltage across the heterostructure.

(9.55)

The terms in the parenthesis are all fixed for a particular device structure and are defined as a threshold voltage or off-voltage V_T. At an applied gate bias V_GS equal to V_T, where E_F ≤ E₀, the 2DEG vanishes.

(9.56)

The Fermi level energy E_F is usually small compared with other terms and can be neglected. Finally, the distribution of the 2DEG in the triangular QW has a peak at a distance of ΔW from the heterojunction interface. The effective depletion layer thickness should be corrected as (W_d +ΔW). For the values of N_S between 5×10¹¹ cm⁻² and 1.5×10¹² cm⁻² in AlGaAs/GaAs HEMTs, ΔW is about 80 Å. The final expression of the sheet carrier density becomes

(9.57)

This equation indicates that the 2DEG density is linearly proportional to the gate bias, V_GS. This linear relationship is limited by two extremes, N_S = 0 and , as illustrated in Fig. 9.24.

Fig. 9.24

Energy band diagram of a depletion-mode HEMT under different gate biases. a V_GS < V_T such that the channel is turned off. b Under a high forward gate bias, the 2DEG is saturated

In a HEMT structure with a 2DEG created at zero gate bias, the Fermi level is positioned above the ground state, E₀. By applying a reverse gate bias, as shown in Fig. 9.24a, the rise of the total Schottky barrier potential energy at the surface leads to a lowering of E_F, which reduces the sheet charge density. When the gate bias is equivalent to the threshold voltage, V_T, the conduction channel is turned off. On the other hand, as shown in Fig. 9.24b, under forward gate bias condition, the rising Fermi level allows more electrons to be transferred into the triangular QW, contributing to the current conduction. This process will continue until all donors in the barrier are ionized. The 2DEG sheet carrier density becomes saturated with further increasing of V_GS.

Figure 9.25 shows the experimental results of N_S as a function of gate bias in several Al_0.3Ga_0.7As/GaAs HEMT samples with different spacer layer thicknesses. All samples have a doping concentration of N_d = 4.6×10¹⁷ cm⁻³ in the barrier layer, except sample No. 76 (N_d = 9×10¹⁷ cm⁻³). It is clear, in all samples, that N_S increases linearly with increasing V_GS and saturates at a higher gate bias voltage. The flat saturated region indicates the maximum achievable sheet carrier density in that sample. By extrapolating the linear part of the V_GS − N_S curve to zero sheet concentration, the threshold voltage is determined. Obviously, the threshold voltage is dependent on the spacer layer thickness due to the V_P term involved, which depends on the spacer layer thickness. As expected, for the same device structure, the thinner the spacer layer, the higher the saturated 2DEG density.

Fig. 9.25

Measured gate-voltage dependence of the sheet carrier density of 2DEG in the GaAs/AlGaAs system. W_sp represents the spacer layer thickness in each sample. All samples have N_d = 4.6 × 10¹⁷ cm⁻³ except sample No. 76, which has N_d = 9.2 × 10¹⁷ cm⁻³.

Reprinted with permission from [6], copyright AIP Publishing

The channel conduction current density of a HEMT is primarily determined by the sheet charge density, which is controlled by the difference between gate bias voltage and threshold voltage. A closer examination of the threshold voltage reveals that it depends on the layer thickness. For a HEMT structure, ϕ_m and ΔE_c are fixed and E_F is relatively small. The major term controlling V_T is , which mainly depends on W_d. Therefore, one can design the operation mode of the device by selecting the proper barrier thickness as shown in Fig. 9.26. For example, a thick barrier (large W_d) leads to a larger V_P and a more negative V_T. A conduction channel is formed in such a HEMT structure even at zero gate bias (Fig. 9.26a). One has to apply a gate bias equal to V_T to completely deplete the 2DEG, thus forming a depletion-mode (normally-on) HEMT. When the barrier layer is reduced to a point such that the Fermi level is well below the ground state (E₀) of the triangular QW at zero bias, V_T becomes positive. A positive gate bias is required to induce the 2DEG for current conduction, and the HEMT is an enhancement-mode (normally-off) FET (Fig. 9.26b).

Fig. 9.26

Schematic band diagram at V_GS = 0 for a normally-on and b normally-off HEMTs

9.4.3 Current and Voltage Characteristics of HEMT

The drain–source conduction current can be expressed similarly as in a MESFET.

(9.58)

where Z is the gate width, N_S is the 2DEG density, and υ_d(F) is the electron drift velocity. Since there is a voltage drop, V_x, between source and drain, it should be included in the N_S expression of (9.57) as

(9.59)

Depending on the field strength, the drift velocity along the conduction channel can be modeled with a linear region and a saturation region with the critical field intensity, F_C, as the deflection point in the υ_d versus F plot.

(9.60)

In the linear region (F < F_C), let :

(9.61)

Since the conduction current in the channel remains constant under a fixed drain bias, the total current can be calculated through integration along the channel length, L.

(9.62)

Thus, the drain current as a function of drain voltage under fixed V_GS is expressed as

(9.63)

At very low drain bias, the /2 term is very small and can be neglected. The drain current is linearly proportional to the drain bias. At a sufficiently high drain bias, the /2 term becomes significant and leads to a sublinear I_DS-V_GS characteristic. Further increasing the drain bias, the drain current becomes saturated.

The effectiveness of current control by the gate bias voltage is determined by the transconductance, g_m. At a fixed V_DS, g_m is calculated as the variation of drain current per gate bias change.

(9.64)

It is clear that large low-field electron mobility and a short channel length are required for a HEMT to achieve a high g_m at a fixed V_DS. Within the linear region, g_m increases with increasing V_DS.

In the saturation region (F ≥ F_C), the drift velocity does not increase with the electric field but has a constant value called the saturation velocity, υ_sat. Therefore, the current becomes a constant, I_DS(sat) = qZN_sυ_sat and

(9.65)

From this equation, the threshold saturation voltage is calculated as V_DS(sat) = V_GS − V_T. Using this relation in I_DS, the I–V characteristic in the saturation region is expressed as

(9.66)

where is the capacitance per unit area in the barrier. The transconductance in the saturation region can also be derived as

(9.67)

Again, large low-field electron mobility and a short channel length are required to achieve a high g_m in the saturation region.

9.4.4 Microwave Noise Performance

The essential elements of the high-speed performance of HEMTs are very similar to those of conventional MESFETs. Therefore, a common microwave equivalent circuit model can be used for both devices. Consider the case where the FET is operating at a frequency below its cutoff frequency, f_T, at room temperature. The microwave noise performance of the HEMT can be derived from the equivalent circuit by the same classical noise model of the MESFET. The minimum noise figure F_min for the HEMT is described as

(9.68)

where g_m, R_G, and R_S are the transconductance, gate resistance, and source resistance, respectively. K_f is a fitting factor and represents the quality of the channel material. Since all external device parameters for both HEMT and MESFET can be made roughly equal, the noise performance difference between the two devices originates in the K_f difference. It was suggested that the size of K_f is related to excess noise in the drain current, which originates as diffusion noise in the channel. For GaAs MESFETs, K_f ≈ 2. In HEMTs, the electrons are narrowly confined to a quantized state along the interface rather than in a 3D configuration. Monte Carlo simulations indicated much lower diffusion coefficients as a function of electric field than those of MESFETs. Experimental K_f for HEMTs have values between 1 and 2. Therefore, HEMTs have a better microwave noise performance than MESFETs. In addition, since f_T can be much higher for HEMTs, we also expect a lower noise figure in HEMTs.

9.5 Optimal Design of the HEMT

Based on discussions above, to achieve high performance, the optimized HEMT structure should incorporate a large ΔE_c (≥0.5 eV) for high sheet carrier density N_S and high current carrying capability; furthermore, materials with high electron mobility should be selected for efficient high-speed operation, and small gate length (L_g < 0.1 µm) should be used to increase the cutoff frequency. In addition, to enhance electron transfer from the barrier into the triangular QW, a small spacer layer thickness (W_sp ~ 25 Å) is preferred. However, in practice, it was not straightforward to realize all these requirements in the early development of HEMTs. Specifically, the DX center problem severely limited the use of Al_xGa_1−xAs with high aluminum content (x ≤ 25%) in the HEMT design. In addition, when increasing the barrier doping level to achieve higher 2DEG density, parallel conduction from free electrons trapped in the barrier and 2DEG could form. To overcome these problems, a pseudomorphic layer and delta-doping designs are incorporated to increase ΔE_c and 2DEG density.

9.5.1 DX Center in Si-Doped AlGaAs/GaAs HEMT and Delta Doping

As discussed in Chap. 4, Si-dopants in AlGaAs can take different crystal configurations: interstitial (relaxed state, DX center) or substitutional (excited state). The DX center is a deep trap that requires different energies for capture and emission of electrons. Further, the finite capture barrier makes it difficult to achieve equilibrium at low temperature (<150 K). Depending on the external excitation, the free electron concentration can have different values. For example, in an Al_0.32Ga_0.68As/GaAs MD structure, the carrier concentration determined by Hall measurement under dark as a function of temperature is shown as solid circles in Fig. 9.27. Upon illumination with a light of energy below the fundamental bandgap of Al_0.32Ga_0.68As at low temperature, the carrier concentration increases to a high value shown as the open circles. The increase in carrier concentration persists and does not return to its dark value even after the illumination has been turned off. This phenomenon is known as the persistent photoconductivity (PPC) effect. The carrier concentration remains high even hours or days after termination of the photo-excitation. The high PPC carrier concentration can be quenched by heating the sample to a temperature higher than 150 K. In Si-doped AlGaAs/GaAs HEMT structures, DX centers can cause anomalous device behaviors including threshold voltage shifts and ‘collapse’ of I–V characteristics (Fig. 9.28). These properties degrade the HEMT performance severely and make the device unreliable.

Fig. 9.27

Dependence of the Hall electron concentration in n-type Al_0.32Ga_0.68As:Si on reciprocal temperature. Solid and open circles indicate experimental data measured in the dark and after illumination at low temperatures, respectively.

Reprinted with permission from [7], copyright AIP Publishing

Fig. 9.28

I–V characteristics of a HEMT at 77 K under illumination and in darkness. The degradation of the characteristics upon the elimination of light occurred gradually over a period of 20–30 s.

Reprinted with permission from [8], copyright IEEE

The origin of the DX center problem is closely related to the ionization energy of Si donors in Al_xGa_1−xAs, which is shown in Fig. 9.29. For Al-composition of x ≤ 20%, the Si donor behaves like a shallow donor (E_d ≤ 5 meV) and no DX center related problem is observed. For x ≥ 30%, the ionization energy of the Si donor rises rapidly to ≥120 meV such that it acts like a deep donor and causes DX center problems.

Fig. 9.29

Thermal ionization energy of the Si donor as a function of the Al mole fraction in Al_xGa_1−xAs.

Reprinted with permission from [7], copyright AIP Publishing

For example, in an Al_xGa_1−xAs/GaAs HEMT with a composition of x = 30%, the donor level, E_d, is 0.12 eV below the conduction band. Since E_d is very deep, under dark, a portion of the donor level inside the barrier is below the Fermi level and stays neutral (unionized). Only a thin-doped barrier layer adjacent to the spacer layer is contributing electrons to the 2DEG channel and the sheet charge density is very low. The neutral layer in the barrier also decouples the 2DEG and the surface. Therefore, N_S in 2DEG is independent of bias! When illuminated with a light source having energy less than the bandgap, electrons are excited out of DX centers. All the donors are ionized and the 2DEG has risen. Due to the finite electron trapping barrier height, there are free electrons remaining in the barrier at low temperatures and these form ‘parallel conduction’ channel in addition to the 2DEG conduction.

Since the ionization energy of Si dopants increases rapidly with increasing Al-composition in AlGaAs-based HEMT structures, ΔE_c cannot be increased much beyond 20%. To achieve a high sheet charge density, increasing the doping level of the AlGaAs barrier layer is the other alternative. But a large and excessive N_d can lead to gate leakage and parallel conduction, which degrade the device performance. One simple solution to this problem is to use a planar (pulse or delta) doping scheme. The doping impurities are all deposited on the same growth plane such that the impurity distribution is confined in a sheet layer. Since the barrier is undoped except for the doping sheet, the band profile shows a straight line-like variation (Fig. 9.30). The planar-doped sheet locates at the minimum of the conduction band profile in the barrier. Since the AlGaAs barrier layer is undoped, it not only solves the gate leakage and parallel conduction problems but also minimizes the DX center-induced complications of the HEMT structure.

Fig. 9.30

Schematic energy band diagram of Si-planar doping in a MD structure

9.5.2 Pseudomorphic High-Electron-Mobility Transistors (pHEMT)

Since N_S in 2DEG is in proportion with the conduction band discontinuity (ΔE_c) at the heterojunction, a large ΔE_c is essential for a high sheet electron density. In AlGaAs/GaAs HEMTs, we cannot increase ΔE_c by increasing the Al-composition much beyond 20% due to the DX center problem. This limitation can be relaxed by using a thin layer of strained InGaAs to replace GaAs at the heterojunction as the 2DEG conduction channel layer (Fig. 9.31). The ΔE_c increases almost linearly with increasing In composition. The amount of indium composition in the InGaAs layer grown on GaAs is limited only by the critical layer thickness such that no dislocations are generated in the channel layer. This type of strained layer HEMT structure is called the pseudomorphic HEMT or pHEMT. The other advantage of using InGaAs as the conduction channel is the associated electron mobility which is higher than that of GaAs. These advantages make AlGaAs/InGaAs pHEMT the most commonly used device in high-speed applications. To further enhance the high-speed operation properties beyond AlGaAs/InGaAs pHEMT, the AlInAs/InGaAs/InP material system is preferred due to the high electron mobility of the In-rich InGaAs channel material.

Fig. 9.31

a Schematic of InGaAs/AlGaAs pseudomorphic HEMT. b Conduction band diagram of the pHEMT

9.6 GaN-Based HEMT Structures

The rapid expansion of wireless communications worldwide has increased the demand for high-power electronic devices in both terrestrial base stations and satellite communication systems. Current GaAs-based FETs have been dominating the market for many years, but the increase in demand calls for devices with higher power operation capacity at microwave frequencies. Among all semiconductors, the GaN-based material system has shown great potential in high-power and high-frequency device applications. Some of the key device properties of GaN- and GaAs-based HEMTs are compared in Table 9.2. Because of their high breakdown voltages, GaN-based HEMTs are ideal for high voltage operation, reducing the need for voltage conversion. This makes device integration much simpler. Another attractive fact is that GaN has a high saturation electron velocity suitable for high-frequency operation. Its great thermal conduction properties and large maximum 2DEG density (≥10¹³/cm²) translate into much higher power densities, making it ideal for high-power operation. In addition, GaN devices can also operate at higher temperatures than their GaAs counterparts because of the higher energy bandgap (~3.4 eV). All these properties make the GaN-based HEMT an ideal candidate for high-power operation at microwave frequencies. However, there are major differences between GaN-HEMT device structures and those of other III–V HEMTs. First, no doping in the AlGaN barrier layer is needed to generate the 2DEG in the GaN channel layer and, second, the generation of the 2DEG is heterostructure dependent.

Table 9.2

Material parameters of GaN and GaAs

Material parameters	GaN	GaAs
Bandgap energy (eV)	3.438	1.424
Maximum sheet electron density (cm−2)	1–5 × 1013	2–3 × 1012
Breakdown field strength (105 V/cm)	50	4
2DEG mobility (cm2/V s)	2000	8500
Saturation electron velocity (107 cm/s)	2.5	1.0
Thermal conductivity (W/cm K)	≥2.1	0.44

9.6.1 Polarization-Induced Sheet Charges at Heterojunctions

GaN-based HEMT layer structures are currently grown using either MBE or MOCVD. MBE layers are usually grown directly on (0001) sapphire or c-Al₂O₃ under Ga-rich surface conditions to achieve a high layer quality. This particular MBE growth condition yields N-terminated B-face or N-face layers, i.e., the GaN growth direction is along [000] capped with a top nitrogen plane (Fig. 9.32). In the MOCVD approach, a low-temperature-grown AlGaN nucleation layer on (0001) sapphire is needed before the growth of GaN. The nitrogen-rich growth condition for the nucleation layer yields a Ga-terminated A-face or Ga-face layer and a growth direction along [0001] capped with a top gallium plane. This growth direction is opposite to the MBE-grown nitrides and causes a sign change in spontaneous polarization.

Fig. 9.32

Schematic diagram of the crystal structure of wurtzite Ga-face GaN.

Reprinted with permission from [9], copyright AIP Publishing

Using an III–N heterostructure grown by MOCVD as an example, we can examine contributions of spontaneous polarization and piezoelectric polarization in the structure to the generation of 2DEG at hetero-interfaces. An AlGaN/GaN heterostructure is grown on c-Al₂O₃ with a thin AlGaN nucleation layer deposited first. The GaN channel layer is grown next and finished by depositing a thin Al_xGa_1−xN barrier layer. The whole heterostructure is intentionally undoped. Since MOCVD-grown AlGaN has a Ga-face surface, P_SP is pointing in the [000] direction toward the substrate and has a negative value for all compositions. Here we assumed the polarization along the c-axis or [0001] toward surface is positive. The AlGaN/GaN heterostructures grown by MOCVD and MBE and their polarization components are shown in Fig. 9.33. The magnitude and sign of P_PE depend on the strain condition. The thick GaN channel layer is relaxed and has a zero piezoelectric polarization component. Since AlGaN has a smaller lattice constant than GaN, the thin AlGaN barrier layer is under tensile strain and P_PE has a negative value. Therefore, the net polarization P is negative at the AlGaN/GaN interface. If the polarity flips over from Ga-face to N-face in structures grown by MBE, both P_SP and P_PE change their signs.

Fig. 9.33

Polarization-induced sheet charge density (σ) and directions of the spontaneous (P_SP) and piezoelectric (P_PE) polarization in Ga- and N-face tensile strained AlGaN/GaN heterostructures grown by MOCVD (left) and MBE (right).

Reprinted with permission from [9], copyright AIP Publishing

Associated with a nonzero polarization P= P in a dielectric slab is an induced internal electric field F, which is produced by the fictitious surface charge density  , where is the surface unit vector. By Gauss’ law, the electric field between the plates produced by these charges is . In analog, the net polarization change within the AlGaN/GaN bilayer heterostructure under discussion induces sheet charge densities at the hetero-interface and on the surface of AlGaN defined as

(9.69)

In this heterostructure, the top surface of AlGaN and the underneath AlGaN/GaN hetero-interface carry −σ and +σ, respectively. During the cooling process, after the epitaxial growth, the polarization-induced positive sheet charge, +σ, will attract free electrons to compensate it and form a 2DEG at the hetero-interface. If the heterostructure is grown by MBE, resulting in an N-face material, the piezoelectric polarization, along with the spontaneous polarization, changes its sign. A negative sheet charge, −σ, will form at the AlGaN/GaN hetero-interface and attract holes. To utilize the fictitious positive sheet charge to induce 2DEG on the AlGaN surface, a GaN layer is needed on top of the AlGaN/GaN heterostructure.

9.6.2 Sheet Carrier Concentration of 2DEG

When Schottky gate contact is made to the surface of the AlGaN barrier layer, the heterostructure with a Ga-face surface forms a HEMT structure. The equilibrium energy band diagram and sheet charge density (σ_i) of the HEMT structure are shown in Fig. 9.34. At equilibrium, due to the band bending across the barrier layer, the Schottky barrier induces an electric field in AlGaN and a net charge density is required to terminate the electric field. The size of the electric field is fixed by the potential drop in the AlGaN determined by the Fermi level position at the surface and at the hetero-interface. Thus, the 2DEG density at the hetero-interface departs somewhat from the polarization-induced electron density. The modified 2DEG carrier density is expressed as

Fig. 9.34

Band diagram of an AlGaN/GaN HEMT structure grown on Ga-face GaN. The sheet charge density distributions in the structure are also shown. σ_p, σ_2DEG, and σ_s are induced piezoelectrical, 2DEG, and surface charge densities, respectively

(9.70)

where σ_p is a piezoelectrically induced charge density at the AlGaN/GaN interface, is the dielectric constant of AlGaN barrier, d is the barrier thickness, qϕ_m is the Schottky barrier height of a gate contact, ΔE_c is the conduction band offset at the AlGaN/GaN interface, and E_F is the Fermi level with respect to the GaN conduction band-edge energy. To determine the net sheet charge density from the polarization-induced 2DEG, we use the following approximations.

For Al_xGa_1−xN, ΔE_c(x) ≈ 2.12x and E_g(x) = xE_g(AlN) + (1–x)E_g(GaN) − 0.7x(1–x). The dielectric constant is expressed as (x) = 9.5 − x, and qϕ_m(x) = 1.3x + 0.84 (eV). The Fermi energy has the form of

(9.71)

where E₀(x) is determined from the Airy function and m*(x) = 0.22m_e. Using the piezoelectric-induced sheet charge density expression of

and polarizations from (7.​128) to (7.​131)

the 2DEG density can be obtained.

Figure 9.35 displays the calculated 2DEG sheet charge density as a function of Al-composition x for 10, 20, and 30 nm AlGaN barriers using parameters available at the time of report [9]. Nevertheless, the results give a meaningful insight into and design guidelines for the AlGaN/GaN HEMT. They show that the piezoelectric effect leads to the formation of a high-density 2DEG (~10¹³ cm⁻²) in AlGaN HEMT structures without intentional doping. In fact, the sheet charge densities in nominally undoped nitride HEMTs can be comparable to those achievable in doped-channel FET structures, but without the degradation in mobility resulting from the presence of ionized impurities in the channel. The 2DEG sheet charge density can go even higher by increasing the Al-composition x in the barrier layer. However, for high crystal quality, the large lattice-mismatch between AlN and GaN prevents it from using x ≥ 40% in the Al_xGa_1−xN barrier. On the other hand, for x < 15%, the conduction band offset becomes too low to confine the 2DEG. Therefore, an optimal composition of Al_xGa_1−xN barrier for maximum 2DEG sheet charge density is limited to 0.15 < x < 0.4. The inset compares the maximum sheet charge density of a pseudomorphic grown Ga-face AlGaN/GaN and an N-face GaN/AlGaN heterostructure. The figures show similar trends in the useful composition range.

Fig. 9.35

Sheet carrier concentration of the 2DEG confined at a Ga-face GaN/AlGaN/GaN or N-face GaN/AlGaN/GaN interface for different thicknesses of the Al_xGa_1−xN barrier. The inset shows the maximum sheet carrier concentration of a pseudomorphically grown Ga-face AlGaN/GaN and an N-face GaN/AlGaN heterostructure.

Reprinted with permission from [9], copyright AIP Publishing

Since the 2DEG in AlGaN HEMT structure is generated by polarization, it requires a minimum strain in the AlGaN barrier, which can be controlled by adjusting the composition and/or the layer thickness. The higher Al composition x in AlGaN causes a larger strain leading to a greater polarization as well as a greater conduction band-edge discontinuity. Therefore, the resultant 2DEG density increases with increasing x for a fixed barrier thickness. On the other hand, for a fixed x, the lattice-mismatch-induced strain increases with the barrier layer thickness, which, in turn, increases the polarization. As shown in Fig. 9.36, for x = 0.27, the induced 2DEG sheet charge density becomes significant only after the barrier thickness is larger than ~5 nm and increases rapidly thereafter. However, the 2DEG density also depends on the efficiency of carrier transfer across the undoped AlGaN barrier, and it prefers a thin AlGaN for easy transfer of sheet charges. Thus, the barrier layer thickness increases beyond ~15 nm, the 2DEG sheet charge density does not increase appreciably and saturates gradually.

Fig. 9.36

2DEG sheet carrier density in the Al_0.27Ga_0.73N/GaN structures as a function of AlGaN barrier width.

Reprinted with permission from [10], copyright AIP Publishing

Now, we have to answer the question: Where do those high-density 2DEG carriers come from in such an undoped structure? Experiments have been carried out to rule out the possibility of the residual impurities in the undoped heterostructure as the source. It turns out that the donor-like surface states E_ss located ~1.5 eV below the conduction band edge of the AlGaN are the source of the 2DEG, as seen from the band diagrams shown in Fig. 9.37. In an AlGaN HEMT structure with a very thin barrier, the energy band edge maintains a near flat band configuration and E_F ≫ E_ss. No 2DEG is formed. When increasing the AlGaN barrier thickness, a greater potential drop is developed and the surface E_ss increases accordingly. For thin AlGaN barriers, E_ss is still below E_F and no 2DEG forms (Fig. 9.37b). Only after the AlGaN barrier thickness reaches a threshold such that E_ss ≥ E_F and electrons associated with the donor-like surface states are ready to transfer to the hetero-interface does the 2DEG form (Fig. 9.37c).

Fig. 9.37

Schematic diagram showing the development of the band structure in AlGaN/GaN samples with increasing AlGaN barrier width.

Reprinted with permission from [10], copyright AIP Publishing

9.7 Heterojunction Bipolar Transistors (HBTs)

9.7.1 Introduction

The idea of using heterostructure at the emitter–base junction in a bipolar junction transistor (BJT) is not new. It was pointed out and patented by William Shockley at the time of the invention of the bipolar transistor at Bell Labs that a large bandgap emitter can be used to increase the efficiency of the device. US Patent 2,569,347 issued to W. Shockley (filed on June 26, 1948; expired on Sept. 24, 1968) claimed.

Claim 2

“A device as set forth in claim 1 in which one of the separated zones is of a semiconductor material having a wider energy gap than that of the material in the other zones”

Herb Kroemer proposed the first heterojunction bipolar transistor (HBT) structure in 1957 [11]. Like other heterostructure devices, the HBT technology has been progressing rapidly only after the material growth technologies were matured. Currently, the highest operation frequency of f_T > 800 GHz has been demonstrated in InP/InGaAs HBTs [12]. New functions, such as high-speed spontaneous and stimulated light emission, have also been demonstrated in HBTs (light-emitting transistors and transistor lasers) [13].

The HBT inherits all the advantages of the BJT including high cutoff frequency due to the short transient time across the thin base region, uniform turn-on voltage which is determined by the built-in potential of the junction, high power capability resulting from the entire emitter area conducting current, and high transconductance which enables low-power applications. By adding a heterojunction to the BJT, additional advantages emerge. The energy band discontinuity at the emitter–base (EB) heterojunction of a HBT suppresses the diffusion of majority carriers from the base into emitter for higher gain. The EB heterojunction also allows the use of a highly doped base region for low base sheet resistance without lowering gain. This means a very thin base layer can be used for a shorter transient time to achieve a higher cutoff frequency. It is expected that HBTs have higher current gain and cutoff frequency than BJT.

At the onset of HBT development, only one heterojunction was used at the EB junction of a single heterojunction bipolar transistor (SHBT). The emitter region of the GaAs-based SHBT is replaced by a larger bandgap AlGaAs, and the base–collector (BC) junction remains a GaAs homojunction. To enhance the breakdown voltage performance of a HBT, a larger bandgap material, such as AlGaAs, is used in the collector region. In this case, both EB and BC junctions are replaced by AlGaAs/GaAs heterojunctions to form a double-heterojunction bipolar transistor (DHBT). Currently, HBTs using different material systems have been developed including In_xGa_1−xP/GaAs, InP/In_xGa_1−xAs, Si/Si_xGe_1−x, and InP/GaAs _xSb_1−x for various applications. Obviously, heterojunctions with either type-I or type-II energy band discontinuity can be used in HBT designs.

9.7.2 Basic Theory of Heterojunction Bipolar Transistors

The energy band diagram of a type I N-p⁺-n SHBT under normal operation is shown in Fig. 9.38. To generalize the discussion, the hetero-interface of the HBT is graded such that the effect of the EB junction energy spike in the conduction band is neglected. The energy bandgap of the emitter and base are E_gN and E_gp, respectively. A forward bias voltage of V_EB and a reverse bias voltage of V_CB are applied to EB and BC junctions, respectively. The terminal currents of the SHBT are the emitter current I_E, base current I_B, and collector current I_C. These currents are related to internal current components of the injected electron current into base (I_n), the injected hole current into emitter (I_p), the saturation current at the EB junction (I_s), and the recombination current in the base region (I_r) through the following equations:

Fig. 9.38

Energy band diagram of an N-p-n HBT, under normal mode operation, showing the various current components and the hole-blocking effect of the valence band discontinuity ΔE_v at the EB junction

(9.72)

The above discussions can also apply to BJTs by simply setting E_gN = E_gp. The ratio of the collector current and base current defines the current gain of the junction transistor.

(9.73)

To maximize β, the components in the numerator and denominator need to be maximized and minimized, respectively. The maximum current gain (β_max) is simply the ratio I_n/I_p in the limit of negligible recombination losses. Assuming a non-degenerate case, the approximate injection electron and hole current densities at the EB junction are

(9.74a)

(9.74b)

where N_E and p_B are the doping level in the emitter and base, respectively; υ_nB is the electron mean velocity in the base near the EB junction; υ_pE is the hole mean velocity in the emitter near the EB junction; and qV_N and qV_p are the potential barrier height for electrons and holes, respectively. At the heterojunction, q(V_p − V_N) = E_gN − E_gp = ΔE_g, we obtain the maximum current gain (β_max)

(9.75)

The mean velocity ratio of (υ_NB/υ_pE) is the least subject to manipulation. To achieve large β_max (>100), it is necessary that either N_E ≫p_B or ΔE_g > kT. Energy gap differences that are several kT are readily available. Due to the exponential nature of the (ΔE_g/kT) term, it dominates β_max even if N_E < p_B. Therefore, using heterojunction structures with large ΔE_g, very high maximum current gain can be achieved regardless of the emitter-to-base doping ratio. It simply means that the hole injection current I_p is sufficiently suppressed by a large ΔE_v and becomes a negligible part of the base current compared to the two recombination currents: I_B ≈ I_s + I_r. If we approximate I_E by I_n, we obtain

(9.76)

In a HBT with a highly doped base, the recombination current I_r is the dominant current component since the saturation current I_s ≪ I_n for a high-quality interface. At the same time, the very high doping density translates into a rather short minority carrier lifetime in the base region. Therefore, the bulk recombination current I_r, rather than the interface recombination current I_s, will dominate the base current. Thus, I_B ≈ I_r and equals the total minority carriers (Q_n) stored in the base divided by the minority carrier lifetime (τ_n):

(9.77)

where A is the cross-sectional area of the EB junction and W_B is the base width of the device. The current gain of a HBT structure with a large ΔE_g and high quality interfaces becomes

(9.78)

The effect of the base doping on the minority carrier lifetime and the base width in turn directly affects the current gain. Even if for heavy base doping levels the lifetimes may be short, high β’s should be achievable in HBTs with sufficiently thin base region. Furthermore, in a thin base HBT, the electron velocity is likely to approach its saturation velocity of ~10⁷ cm/s, enhancing the current gain. As a result, no serious concerns arise from reduced minority carrier lifetime in HBTs with heavily doped thin (≤ 100 nm) base region.

Now we can examine the current gain property of a BJT. In homojunction bipolar junction transistors, ΔE_g = 0. The only way to achieve high current gain is to make N_E ≫p_B. Since the base doping level is kept low, it requires a thick base layer to minimize the base sheet resistance. A thick base layer will eventually limit the cutoff frequency of the BJT. On the other hand, the doping level in the emitter cannot exceed certain limits. A heavily doped emitter will cause other problems. When the emitter degenerates, the Fermi level can move into the conduction band and cause bandgap shrinkage. This is equivalent to a reduction of conduction band discontinuity at the EB junction or ΔE_g < 0. A lowering of β_max is expected. Therefore, the HBT takes advantage of the exponential dependency of ΔE_g to achieve high gain with high base doping concentration. Furthermore, the doping profile of the BJT is graded due to diffusion and/or ion implantation processes used in device fabrication. For HBTs, a much sharper doping profile is achieved by controlling doping properties during epitaxy. The abrupt and heavily doped base region is desirable for achieving high current gain and high cutoff frequency in a HBT. Thus, it is critical to use a suitable p-type dopant that possesses a high doping efficiency and a low diffusivity. For GaAs-based HBTs, carbon has proved to be an ideal p-type dopant among other common candidates such as Zn and Be. It can be easily doped to over 10²⁰ cm⁻³ in many III–V compound semiconductors with negligible out-diffusion. However, carbon atoms are hard to generate from a solid source, such as graphite, due to their extremely low vapor pressure. Currently, the heavily p-type carbon doping is conveniently achieved using gaseous carbon sources such as CCl₄ (in MOCVD) and CBr₄ (in MBE).

The current gain of a BJT and HBT is commonly measured using the Gummel plot scheme [14]. A Gummel plot shows the base and collector currents as functions of V_BE when V_CB = 0. The ratio of the measured I_C/I_B at various V_BE gives the current gain. For the ideal case, both I_B and I_C are dominated by diffusion current component and proportional to exp(qV_BE/kT). We expect a constant gain independent of bias. In real devices, defects and other recombination centers at the EB hetero-interface and in the bulk of the base lead to a non-ideal base current with an exp(qV_BE/mkT) dependence. The parameter m is referred to as the ideality factor and has a value between 1 (dominated by diffusion current) and 2 (dominated by generation-and-recombination current I_s). Therefore, the EB junction property can be determined by the ideality factor (m) of I_B. For example, Fig. 9.39 shows the Gummel plot of an InGaP/GaAs DHBT with an emitter size of 60 × 60 µm². At low current, m = 1.84 (~2), I_B is mostly due to the generation-recombination current in the depletion region of the EB junction and I_s is larger than I_r. At mid-to-high current, m = 1.15 (~1), showing that the bulk recombination current (I_r) in the base region becomes dominant due to its high doping level. The base current eventually departs from m ~ 1 due to the large voltage drops across the parasitic base and emitter resistances, causing the available junction voltage to decrease. For the collector current, it increases with V_BE with an ideality factor of m = 1.07, a value which is close to unity.

Fig. 9.39

Gummel plot for InGaP/GaAs HBT. The emitter size of the HBT is 60 × 60 µm².

Reprinted with permission from [15], copyright IEEE

9.7.3 Band Discontinuity of Heterostructures

In a type-I heterostructure, a ‘spike-and-notch’ energy band diagram generally appears at the abrupt heterojunction due to the conduction band discontinuity ΔE_c as shown in Fig. 9.40 for a SHBT. This energy spike can be removed by using a graded composition in the large bandgap emitter near the hetero-interface as used for discussions in the previous section. The existence of the energy spike at the EB junction of an abrupt HBT can modify the current conduction across the heterojunction. Using the simple thermionic emission model, the magnitude of forward current depends on the amount of electrons having enough energy to surmount the potential barrier. In an abrupt HBT, the potential barrier for electrons is simply V_N. However, in a graded HBT, the effective potential barrier becomes (V_N − ΔE_c/q) since the energy spike, ΔE_c, has been eliminated by the graded composition design. Therefore, under the same bias condition, the collector current of the abrupt HBT, I_n(abrupt), is reduced from the graded HBT, I_n(graded), by a factor of

Fig. 9.40

Energy band diagram for HBT with abrupt emitter–base junction

(9.79)

Since the current gain is proportional to exp(ΔE_g/kT) in the graded junction case, the current gain of abrupt HBTs is modified by reducing ΔE_c from ΔE_g in the injection current relation (9.75). Thus

(9.80)

It is clear that a large ΔE_v is preferred in abrupt N-p⁺-n HBT structures for a high current gain.

The existence of the energy spike in the conduction band at the EB heterojunction has other effects on device performance. A beneficial effect is that electrons injected from emitter into the base have to overcome the EB junction barrier with higher potential energy and become hot electrons with high saturation velocity. The improved travel speed across the base region leads to a reduced base transient time for high frequency operation. A detrimental effect is that the energy spike can block current flow at bias voltages V_CE < ΔE_c/q = V_off, which is the offset voltage. Also, the triangular QW formed on the base side of the EB junction can trap electrons that lead to an enhanced recombination at the junction. Therefore, the current gain will be reduced due to an increasing I_r.

Next, we turn our attention to the BC junction. In a SHBT, the same semiconductor is used for both base and collector and the BC junction is a homojunction. Therefore, the same arguments about the BC junction of a BJT can be applied to a SHBT. In DHBTs, the BC homojunction is replaced with a heterojunction. The use of a wide bandgap collector material can improve the power handling capability by the enhanced breakdown voltage. Again, due to the existence of a finite ΔE_c, an energy spike forms at the BC junction as shown in Fig. 9.41. This energy barrier (ΔE_c) impedes free collection of electrons by the reverse-biased BC junction. It will suppress the collector current until a large V_CE is reached to allow collection of electrons by the collector. Thus, it will increase the minority carrier resident time in the base region, which reduces the bandwidth of the device. Therefore, a graded collector junction in the form of composition grading or chirped superlattice structure is usually used to eliminate this problem. For a lattice-mismatched material system such as InGaAs/InP, this will complicate the growth procedures and may cause interface problems leading to a lower current gain.

Fig. 9.41

a Comparison of the I–V characteristics of InGaP/GaAs SHBT and DHBT. The base current was stepped from 0 to 400 µm in 100 µA steps. Reprinted with permission from [16], copyright AIP Publishing. b Current blocking at the base–collector junction of an InGaP/GaAs DHBT

The collector current blocking mentioned above can be totally avoided by using a type-II DHBT design. This design simplifies the growth of the BC junction without using composition grading. In particular, for the InP/GaAs_0.5Sb_0.5/InP DHBT design shown in Fig. 9.42, it provides a nearly zero conduction band offset (ΔE_c = −0.06 eV, E_c(InP) < E_c(GaAsSb)) for a negligible turn-on voltage and no current blocking effect at the BC junction. The large ΔE_v of ~0.62 eV and the use of InP collector material provide a large current gain and large breakdown voltage, respectively.

Fig. 9.42

Energy band diagram of an InP/GaAsSb type-II double-heterojunction bipolar transistor

9.7.4 High-Frequency Operation of HBT

The high-frequency performance of HBTs is fundamentally determined by the stored minority carrier charge in the transistor that has to be removed from (added to) the transistor before it can turn off (on). Hence, the maximum frequency at which the transistor is capable of operating depends on the junction capacitance charging time and charge carrier transit time. In forward active operation, the forward transit time τ_F or the emitter-to-collector transit time τ_EC represents a fundamental limit for the switching speed and maximum frequency of operation of a HBT. The parameter most commonly used to define this maximum frequency of operation is the cutoff frequency f_T. This is the frequency at which the common emitter, small-signal current gain drops to unity under conditions of a short-circuit load.

In practice, parasitic capacitance and resistance of the HBT will slow down the switching of digital circuits and limit the frequency of operation of analog circuits. To include the effect due to parasitic resistances and junction capacitances, the maximum oscillation frequency f_max is a good predictor of transistor performance.

1. (a)

   Emitter-to-collector transit time

    

The emitter-to-collector transit time models the excess charge stored in the HBT under normal operation of a common-emitter configuration. This is an extremely important device parameter, since it sets a fundamental physical limit to the switching speed and maximum oscillation frequency of operation of a HBT. The emitter-to-collector transit time τ_EC can be written as the sum of the individual delay times as well as charging times of junction capacitances in the various regions of the HBT.

(9.81)

where τ_E, τ_B, τ_C, and τ_BC are the emitter delay time, base transit time, collector transit time, and base–collector space-charge layer delay time, respectively. The emitter delay τ_E associates the emitter junction charging time involving the emitter–base junction capacitance C_E and the dynamic emitter resistance kT/qI_C.

(9.82)

The base delay τ_B represents the transport of electrons through the base layer via drift, diffusion, or ballistic transport. In the limit of diffusion current only,

(9.83)

with

Thus,

(9.84)

W_B is the base width, D_nB is the electron diffusion constant, and n_B0 is the equilibrium electron concentration. This result of τ_B is valid for HBTs with a uniform base. If the base is non-uniformly doped or has a composition gradient, then the variation in doping and/or bandgap energy gives rise to a built-in electric field across the neutral base region. This built-in field would aid electron transport across the base and hence reduce the base transient time. This situation can be taken into account by modifying the equation as

(9.85)

where γ is a constant that has a value of 2 ≤ γ ≤ 4.

The collector transit time τ_C corresponds to the transport time through the collector layer, is classically found to be proportional to the collector thickness W_C, and is expressed as

(9.86)

where υ_sat is the electron saturation velocity in the collector, typically measured as 3–4 × 10⁷ cm/s.

The last term τ_BC represents the charging time delay associated with the parasitic BC junction capacitance C_BC. For an incremental input voltage change dV_BE, the BC junction voltage change is

(9.87)

where R_C and R_E are the parasitic collector and emitter resistances, respectively. Therefore,

(9.88)

The total delay associated with a HBT is directly related to the cutoff frequency and can be described as

(9.89)

Since f_T is defined for small-signal conditions, a small-signal circuit model, such as the hybrid-π model, as shown in Fig. 9.43, can be used to derive an expression for f_T. To a first order, the series resistances of three terminals and recombination in the depletion region were neglected. Under the conditions of a short-circuit load, the small-signal collector and base currents can be written as

Fig. 9.43

Small-signal hybrid-π circuit model of HBT

(9.90)

(9.91)

where g_π = 1/r_π (r_π is the equivalent input resistance), ω = 2πf, g_m is the transconductance, C_π is the BE junction diffusion capacitance, and C_µ is the BC junction diffusion capacitance.

The common-emitter current gain can be written as

(9.92)

If we define β₀ = g_mr_π, the equation can be simplified as

(9.93)

At low frequencies, the current gain maintains a constant value of β = β₀. As the frequency increases, the second term in the denominator of the equation becomes large with respect to unity, and β can be approximated by

(9.94)

At high frequencies, β begins to roll off with a limiting roll-off rate of −20 dB/decade (∝1/f). The frequency-dependent gain values are determined from S-parameters measured with microwave network analyzers. The gain values (in dB) as functions of frequency are usually plotted in a semi-log fashion under constant V_CE = V_BE and I_C as shown in Fig. 9.44a. For very high-speed devices, the gain at frequencies exceeding the limit of instrument capacity was obtained by extrapolating −20 dB/decade lines from a best-fit average of the measured current gain.

Fig. 9.44

a RF response and performance figure extrapolations for 0.25 × 16 µm² InP/InGaAs SHBT. Reprinted with permission from [17], copyright IEEE. b f_T and f_max as a function of collector current density of a 0.35 × 8 µm² type-II InP/GaAsSb DHBT. Reprinted with permission from [18], copyright American Vacuum Society

Since τ_EC is a function of the collector current, the cutoff frequency is also a function of the collector current as illustrated in Fig. 9.44b. At low collector currents, the depletion capacitance term (τ_BC) in (9.89) dominates and hence f_T increases with I_C. At medium currents, the transit time terms become larger than the depletion capacitance term, and f_T ceases to rise with collector current. At high collector currents, the cutoff frequency decreases markedly due to high current effects, especially the Kirk effect which will be described later.

The other important high-frequency parameter for a HBT is the maximum oscillation frequency f_max, where the unilateral power gain (U) drops to unity. The unilateral or Mason gain is the maximum gain obtained by conjugate matching of inputs and outputs of the device, together with the use of a lossless feedback network to tune out any internal device feedback. The derived expression of the maximum oscillation frequency is

(9.95)

which shows that the f_max is determined not only by the f_T but also by BC junction capacitance C_BC and the base resistance R_B. It is clear that a high p-type doping concentration in the base region leads to a low base sheet resistance and an improved f_T, both of which enhance the f_max. On the other hand, the increase in f_T due to reduced τ_BC by higher collector doping could increase C_BC and may cause a decrease in f_max, depending on the relative importance of τ_BC in f_T. Therefore, for high-frequency circuit applications, a careful optimization of these two parasitics is required.

1. (b)

   Kirk effect

    

The reduction of f_T at high collector current mentioned in the last section is due to a base widening or Kirk effect. Consider Poisson’s equation in the depletion region of the BC junction:

(9.96)

where p and n are mobile charges and N_d is the fixed (ionized) charges. In the reverse-biased collector of N-p-n HBT structures, and electrons injected from the emitter are transported across the BC junction by drift under high field situations. The electron concentration relates the drift current density J_n by n = J_n/qυ_sat, where υ_sat is the electron saturation velocity. Thus,

(9.97)

This equation indicates that the slope of the electric field intensity depends on the difference of qN_d and J_n/υ_sat. Under low current density, the contribution from the mobile electrons can be neglected and dF/dx is unchanged (Fig. 9.45). At sufficiently large collector current density, the BC depletion region can extend all the way to the n/n⁺ subcollector boundary. For a fixed V_CB, the depleted collector region where the electric field F exists is fixed and dF/dx still maintains a positive slope. With further increasing the collector current density (J_C), the mobile charge in the depletion region becomes significant and cannot be neglected. This leads to a decreasing F with increasing J_C or a decreasing dF/dx slope. At certain J_C, F = 0 and the depleted collector layer turns into a neutral layer. Holes can be injected freely from the base into the adjacent neutral collector region. With the injected holes, the conductivity type of the collector adjacent to base changes from n to p. Thus, the effective base thickness is increased at high collector current density, which degrades the cutoff frequency of the HBT as shown in Fig. 9.44b.

Fig. 9.45

Electric field intensity distribution in the fully depleted collector region under large collector current density. With further increase of collector current density, the slope of the electric field intensity curve changes from positive to negative as indicated by the arrow

1. (c)

   Device scaling and surface passivation

    

Earlier studies of HBTs have shown that a significant component (>75%) of the total device delay was associated with the intrinsic forward delay of the device, primarily the base and collector transit times. Therefore, an effective method to increase the cutoff frequency f_T of the HBT is through vertical scaling of the base and collector epitaxial layers. Vertical scaling strictly involves the design of layer thicknesses, doping levels, and bandgap engineering to reduce device transit time, thereby increasing device bandwidth. Figure 9.46 shows the experimental relationship between vertical scaling and base/collector transit times. The base transit time is clearly illustrated by two slopes. For thicker bases, the classic diffusion transport dominates and is proportional to (W_B)². As the base thickness is scaled below the mean free path for electrons (~30 nm), the ballistic transport dominates with a linear dependence on W_B. However, as the base and collector layers are thinned, parasitic resistances and capacitances also increase—specifically the base resistance, R_B, and the base/collector capacitance, C_BC. The increase of these parasitic components acts to severely degrade the maximum oscillation frequency f_max of the device.

Fig. 9.46

Experimental results on the relationship between vertical scaling of InGaAs/InP SHBT and base/collector transit times

For effective reduction of transit times in HBTs without incurring significant increases in charging delays, vertical and lateral scaling must be simultaneously employed in order for submicron devices to achieve high performance. Lateral scaling refers to device topology design and processing techniques used to reduce parasitic capacitances and resistances to further enhance device speed. Lateral scaling also has the benefit of providing lower power operation and more efficient heat removal; reducing the emitter length lowers the thermal resistance of the HBT, allowing for higher current densities and lower junction temperatures. Figure 9.47 shows the peak f_max and f_T values versus emitter dimensions of InP/InGaAs SHBTs. For the 0.25 µm emitter width (W_E), a 76% improvement in f_max is observed from reducing emitter lengths (L_E) from 12 µm to 1 µm; shrinking the emitter width from 0.4 µm to 0.25 µm results in an l8% f_max increase.

Fig. 9.47

Experimental results on the relationship between emitter lateral scaling of InGaAs/InP SHBT and cutoff frequency

Beyond a certain point, however, scaling has detrimental effects on device performance due to physical limitations imposed by shrinking device dimensions. The significant drop in f_T observed in Fig. 9.47 for emitter lengths 8 µm and smaller on a standard InGaAs emitter cap is attributed to an increase in emitter resistance due to smaller contact areas. Ideally, scaling theory predicts that f_T should remain constant regardless of emitter length. However, the finite cap doping causes large increases in contact resistance for these emitter areas. The emitter cap cannot be doped higher due to solid solubility limits, but emitter contact resistance can be reduced through emitter cap engineering by using a narrow-bandgap cap material such as InAs. InAs provides a better contact material because of the smaller bandgap, higher doping capability, and higher thermal conductivity when compared to a standard InGaAs cap. The utilization of an InAs emitter cap is shown to reduce the emitter contact resistance by a factor of 2 in submicron HBT devices. The contact resistance reduction enhances the scalability of the emitter by allowing the emitter length to scale to dimensions smaller than 4 µm before the f_T degradation occurs. Overall, lateral scaling is often dependent on process maturity, relying on advanced fabrication techniques to counteract the effects of vertical scaling on f_max. Therefore, for HBT development using a new material system, the best indication of the system’s potential is determined by the f_T of the transistor. It is assumed that as the process matures, the power gain of the device will be increased through technological advances.

In general, the HBT has a vertical geometry with an intrinsic device size defined by the emitter contact area. The base contact is designed to surround the intrinsic base region underneath the emitter. Unavoidably, there is an exposed extrinsic base region between the base contact and the intrinsic base area. Consequently, in HBTs made of materials with a high surface recombination velocity (SRV), such as GaAs (SRV > 10⁶ cm/s), some minority carriers injected from the emitter recombine with the base majority carriers on the exposed surfaces resulting in the extrinsic base surface recombination current. This base current component is proportional to the magnitude of the emitter periphery rather than the emitter area. As the size of the emitter is reduced, the emitter perimeter-to-area ratio increases and surface recombination current becomes a major part of the overall base current. The current gain of such a scaled down GaAs–base HBT is substantially reduced from that of a large device whose perimeter-to-area ratio is small. The surface recombination current problem can be reduced by passivating the exposed extrinsic base region that is not directly under the emitter with an emitter ledge as shown in Fig. 9.48. A thin ledge of emitter material left surrounding the emitter mesa can dramatically reduce surface recombination current and improve device scaling. The exposed ledge layer outside the emitter mesa is totally depleted, and no carriers are available for recombination at the surface. Therefore, the base current is not affected and current gain is preserved. On the other hand, the free In_xGa_1−xAs surface shows more ideal surface characteristics with a small SRV of 10³ cm/s for an In composition x ~ 0.5. Therefore, for HBT materials with low SRV such as in InP/InGaAs HBTs, the surface recombination current is not significant even in small devices and the surface passivation is not required.

Fig. 9.48

Cross-sectional drawing of a HBT with emitter ledge passivation. The emitter ledge (hatched area) is totally depleted such that the base current underneath is not affected

9.7.5 Basics of HBT Processing

The design of HBTs is intimately interwoven with the technologies used for their fabrication. Therefore, any study of the HBT would be incomplete without understanding the fabrication technology. A typical HBT process developed at the University of Illinois at Urbana-Champaign (UIUC) is discussed below for either InGaP/GaAs or InP/InGaAs high-frequency HBTs. Other research groups may have developed their own HBT process steps, but the principal ideas discussed below remain the same. The standard InGaP/GaAs HBT structure is a single heterojunction device grown on a semi-insulating GaAs substrate that employs a carbon-doped GaAs base, a lattice-matched InGaP emitter, and a thin InGaAs emitter contact layer. Figure 9.49 shows a series of device profiles detailing the high-speed HBT process sequence. Initially, in Fig. 9.49a, non-alloyed metal contacts are deposited on the InGaAs emitter contacting layer. The cap and emitter material are then selectively chemically etched using the emitter metal as a mask, and this etch is followed by a selective InGaP emitter etch. This etching sequence provides an approximately 0.2 µm undercut beneath the emitter metal, which is necessary for the deposition of self-aligned, non-alloy base contact (Fig. 9.49c). After the base metallization, the base and collector are chemically etched, leaving the subcollector exposed (Fig. 9.49d). Before the collector metallization, an etch of approximately 1000 Å into the substrate is performed to electrically isolate the HBT (Fig. 9.49e). Next, the collector contacts are deposited on the collector mesa and overlap the edge of the isolation mesa (Fig. 9.49f). By allowing this overlap, the active collector contact area near the edges of the mesa is maximized and the collector contact resistance is reduced. The HBT device structure has now been defined. Figure 9.50a shows the scanning electron microscope (SEM) top-view micrograph of a fully fabricated single-finger GaAsSb/InP DHBT with an emitter size of 0.25 × 5 µm².

Fig. 9.49

Cross-sectional diagrams of UIUC HBT process: a post-emitter contact liftoff, b post-base etch, c post-base contact liftoff, d post-collector etch, e post-isolation etch, f post-collector contact liftoff, g post-polyimide/SiN_x passivation, h post-SiN_x via etch, and i post-overlay metal liftoff

Fig. 9.50

Left: Top view SEM micrograph of a fully fabricated GaAsSb/InP DHBT before planarization with an emitter size of 0.25 × 5 µm². Right: Cross-sectional SEM micrograph of a completed GaAsSb/InP DHBT with an emitter size of 0.35 × 5 µm².

Courtesy M. Feng, University of Illinois at Urbana-Champaign

At this point, the HBT has a non-planar topology. In order to make the HBT structure more planar to facilitate both via etching and the formation of planar probe pads for high-frequency testing, a planarization process (Fig. 9.49g) is required. The spin-on polyimide followed by a deposited Si₃N₄ layer completes the planarization process. Contact vias are defined using standard photolithography process (Fig. 9.49h). After the vias have been etched, a 1 µm layer of overlay metallization is deposited to form the probe pads and interconnect metallization. In the last step, an airbridge process is utilized to produce a second level of plated interconnect metallization allowing emitter fingers to connect to common-emitter probe pads. The cross-sectional SEM micrograph of a GaAsSb/InP DHBT with an emitter size of 0.35 × 5 µm² is shown in Fig. 9.50b.

9.8 III–V Metal-Oxide-Semiconductor Field-Effect Transistors

Silicon metal-oxide-semiconductor field-effect transistor (MOSFET)-based integrated circuit (IC) technology is the dominant semiconductor technology used by all electronics industries with a 2018 worldwide sales of over $470 billion. Miniaturization of the feature size of ICs to increase the density of components has been the foundation of the over 50-year-long steady advance of silicon technology. Following Moore’s law, the exponential increase of transistor count per unit area as a function of time has been faithfully delivered by the industry since 1970. The minimum transistor gate length also decreases with time exponentially by incorporating strained SiGe channel material, high-κ gate dielectrics, and non-planar multigate structures (see Fig. 1.​4). Although 5-nm-node CMOS circuits are on the horizon, further reduction of the feature size to below 2 nm will push the device structure into the quantum regime. At that moment, the silicon technology will reach the point at which significant materials and device innovations will be required to further technology developments. One possible solution for the future is the hybrid material system in which silicon, germanium, and III–V compound semiconductors are integrated together on silicon wafers. For example, taking advantage of the very high electron mobility in GaInAs and high hole mobility in germanium, advanced CMOS circuits consisting of n-GaInAs channel and p-Ge channel MOSFETs might be fabricated together on the silicon wafer.

Because of their high bulk electron mobility, III–V MOSFETs have long been pursued in hopes of achieving performance superior to that of their Si counterpart. However, due to the high surface state density, the realization of unpinned surface Fermi level in III–V compound semiconductors had been elusive until two decades ago. In searching for a low defect density, thermodynamically stable gate dielectric, native oxide and deposited oxide using a variety of deposition techniques have been investigated. Unlike the SiO₂/Si system, the native surface species in III–V materials are complicated. For example, the stable oxides of GaAs consist of As₂O₃, As₂O₅, Ga₂O₃, Ga₂O, and GaAsO₄ with different thermodynamic properties. Among all native oxides in this system, the As-oxides are the least stable while Ga₂O₃ is the most stable oxide. When the low-temperature-grown oxides are annealed at higher temperature, the composition of the oxide layer changes significantly. As temperature increases, the less stable As-oxides either evaporate away or are converted to the most stable oxide in the system (Ga₂O₃) along with elemental arsenic located at the interface. The pinning of the Fermi level at the GaAs-oxide interface has been unambiguously correlated with significant amounts of As₂O₃, As₂O₅, and elemental As present in native oxides. In order to fabricate functional III–V MOSFETs, it is necessary to completely remove the surface native oxide first before a stable and robust dielectric can be deposited. Thus, the successful development of III–V MOSFET technology relies strongly on the surface passivation and interface control technology.

9.8.1 III–V Alloy Surfaces and Semiconductor-Oxide-Metal Interfaces

The semiconductor surface state model was first proposed by John Bardeen in 1947 to explain the Fermi level pinning phenomenon at the metal–semiconductor (M–S) interface. It is assumed that the distribution of surface states becomes charge-neutral if the states are filled to a particular energy level, ϕ₀ (above E_V = 0), inside the forbidden gap. In the strong pinning limit, the metal Fermi level is pinned by the interface states at ϕ₀. The pinning energy level ϕ₀ is then the charge neutrality level of the interface states. Since then, two principal models, the intrinsic model of metal-induced gap states (MIGS) and the extrinsic model of defect states, have been developed. In the intrinsic case, a semiconductor in contact with a metal contains intrinsic states inside its band gap which are the evanescent tails of the metal wave function decaying into the semiconductor. These states are the dangling-bond states of the broken surface bonds of the semiconductor and called MIGS. On the other hand, in the extrinsic case, the interface states are introduced near the surface by processing-induced bond disorder (e.g., disorder caused by metal deposition, etching, or chemisorption of oxygen). In general, both types of interface states, MIGS and defects, could cause pinning. However, there is no universally accepted model for the M-S interface. Nevertheless, these studies of M-S contact have enriched our understanding of the chemistry and physics of III–V surfaces, such that III–V-oxide interface models can be developed.

1. (a)

   Empirical CNL model of M-S interfaces

    

In semiconductors, the dangling-bond energy is typically located inside the band gap and the interface trap density (D_it) increases exponentially in the energy ranges close to the band edges. The D_it distribution forms a U-shaped continuum of donor- and acceptor-type states with its minimum, or the pinning energy, located at the charge neutrality level (CNL). The CNL energy level represents a weighted average value over the density of states. CNL is pushed away by the large DOS of the conduction and valence bands from the intrinsic energy level E_i, as shown in Fig. 4.​21. Therefore, the semiconductor surface pinning energy CNL is located inside the forbidden gap for most semiconductors. If the Fermi level E_F is above CNL, the states are of acceptor type and negatively charged if the states are occupied. If the Fermi level E_F is below CNL, the states are of donor type and positively charged if the states are occupied.

The CNL energies can be calculated from their pseudopotential band structures. The CNL values (above E_v = 0) of III–V binaries are determined by averaging values derived from various theoretical models as shown in Table 4.​5. The experimental CNL values of the semiconductors can be extracted from Schottky barrier heights. In general, the calculated CNL is in close agreement with Schottky barrier heights (ϕ_bv) on p-type III–V binary compounds. Thus, one can determine the surface pinning energy of III–V binary and ternary compound semiconductors empirically based on the valence band alignment method developed by S. Tiwari and D. J. Frank (Sect. 6.​1). Figure 9.51 shows the complete room-temperature conduction band-edge and valence band-edge energies as a function of the lattice constant for unstrained III–V compound semiconductors. This is the same figure that Tiwari and Frank derived (Fig. 6.​5) for band discontinuity determination except the zero point of the energy is now representing the charge neutrality level (CNL) or trap neutral level (ϕ₀) for each lattice constant group. In the case of Si, the state-of-the-art SiO₂/Si interface has very low interface trap density of 10⁹–10¹⁰/cm²−eV. Although the energy separation between CNL is ~0.6 eV and ~0.5 eV from the conduction band minimum (CBM) and valence band maximum (VBM), respectively, the Fermi level is unpinned. Thus, high-performance n-MOSFETs and p-MOSFETs are routinely fabricated. In the case of GaAs, CNL is far away from CBM (~0.8 eV) and VBM (~0.6 eV) so that both GaAs n-MOSFET and p-MOSFET are difficult to realize when significant interface traps presented. It is interesting to note that CNL is inside the conduction band of InAs. This indicates that InAs-based n-MOSFETs are easy to realize. For example, T. Brody and H. Kunig, in 1966, demonstrated both enhancement- and depletion-mode MOSFETs using evaporated SiO₂ on InAs film prepared by co-evaporation method. One interesting ternary system is InGaAs where the CBM of In-rich InGaAs intersects CNL at x_InAs ~ 0.75. Thus, In-rich InGaAs n-MOSFET is relatively easy to achieve.

Fig. 9.51

Energy alignment of CNL with the band edges of elemental and III–V semiconductors at MOS interfaces plotted as a function of the lattice constant of semiconductors. For III–V compounds, the circles indicate the band edges of binaries and the lines show the band edges of ternaries

For device applications, the next important issue after unpinning the Fermi level is achieving strong electron inversion in III–V MOSFETs. This can be explained using the distribution of the density of the surface states D_it as a function of the energy as shown in Fig. 9.52. It is assumed that the D_it distribution from VBM to CBM (with energy E_CBM) is nearly parabolic in a logarithmic scale due to the significant interface traps at III–V interfaces. The minimum value of D_it depends on the surface processing techniques. For simplicity, the D_it value at CBM is fixed at 10¹⁴ cm²−eV for all III–V compounds and has a minimum value located at CNL (with energy E_CNL). Assuming the strong electron inversion occurs when the Fermi level reaches CBM, the number of interface-trapped negative charges Q_it can be calculated by integrating D_it from E_CNL to E_CBM. It is obvious that the dominant factor is the energy difference between E_CNL and E_CBM. The built-in negative charges Q_it to prevent a strong inversion charge to participate in transport are larger for the material with a deep CNL below CBM. For example, in GaAs, with the CNL located ~0.8 eV below CBM, it builds up ~10⁻⁶ C/cm² negative charges to prevent a strong inversion charge to participate in transport. In contrast, the CNL and CBM potential difference for In_0.53Ga_0.47As lattice-matched with InP is only 0.27 eV. The built-up negative charge is only ~3.4 × 10⁻⁷ C/cm², a factor of three smaller than that in GaAs. Therefore, it is much easier to realize an inversion-mode In_0.53Ga_0.47As/InP MOSFET than a GaAs MOSFET.

Fig. 9.52

Schematic for the parabolic D_it distribution within energy band of GaAs and In_0.53Ga_0.47As. The CNL is aligned 0.8 eV and 0.27 eV below CBM for GaAs and In_0.53Ga_0.47As, respectively. The shaded area shows the built-up negative charges in interface traps after Fermi level moves from CNL to CBM.

Reprinted with permission from [19], copyright AIP Publishing

1. (b)

   High-κ dielectrics and oxide-semiconductor (O-S) interfaces

    

Scaling of the silicon complementary metal-oxide-semiconductor (CMOS) FET technology is at the center of Moore’s law. The exponential increase of transistor count per unit area as a function of time has been faithfully delivered by the industry since 1970. The minimum transistor gate length also decreases with time exponentially. However, when the feature size is reduced to below 65 nm, the SiO₂ gate dielectric layer becomes so thin (<2 nm) that the gate leakage current due to direct tunneling of electrons through SiO₂ becomes very high. The excessively large leakage current leads to an unacceptably high circuit power dissipation level. The FET is a capacitance-coupled device, where the source–drain current of the device depends on the gate capacitance,

(9.98)

where is the permittivity of free space, κ is the relative permittivity (dielectric constant), A is the area, and t is the thickness of the dielectric SiO₂. Since the tunneling current decreases exponentially with increasing the dielectric thickness, a new dielectric with a larger dielectric constant than that of SiO₂ (κ = 3.9) has to be introduced while maintaining the same capacitance. These non-native new gate oxides are called high-κ dielectrics. In selecting suitable high-κ dielectrics for microelectronics applications, there are several important requirements about their physical properties. First, the κ value must be high enough that it will be used for a reasonable number of years of scaling. A value of κ ≥ 20 is preferred. Second, the oxide must have large bandgap energy and act as an insulator, by having oxide-Si band offsets over 1 eV to minimize leakage current. Third, the oxide must be thermodynamically as well as kinetically stable such that it is compatible with extreme processing conditions. Above all, the selected oxide must form a good electrical interface with the semiconductor, which is dependent on the deposition method. The oxides that satisfy most of these criteria are Al₂O₃, HfO₂, ZrO₂, Y₂O₃, La₂O₃, and various lanthanides (e.g., Gd₂O₃).

For III–V MOSFETs, due to the lack of high-quality native oxides, high-κ dielectrics used in current Si technology are implemented as gate oxides. In order to use these dielectrics as the gate oxide of III–V MOSFETs, the conduction band (CB) offset, ΔE_C, between the dielectric and III–V alloy must be over 1 eV to achieve a low leakage current. The CB offset at the M-S interface has previously been determined by the MIGS method using CNL as a reference energy level. The MIGS model is extended to determine band offsets between oxides and semiconductors. The CB offset is given by

(9.99)

Here Φ_CNL is the charge neutrality level measured from the vacuum level, χ is the electron affinity (EA), and the subscripts o and s represent the oxide and semiconductor, respectively. S is a dimensionless pinning parameter where S = 1 describes the Schottky limit of no pinning and S = 0 describes the Bardeen limit of strong pinning. Empirically, S depends only on the optical dielectric constant of the oxide, , and follows the trend

(9.100)

The CNL energies for high-κ oxides have been derived from the bands calculated by either the tight-binding or pseudopotential method. The calculated CNL energies (above the valence band edge) and measured bandgap energies, electron affinity, and optical dielectric constants of these high-κ oxides are listed in Table 9.3. The calculated band offsets of various high-κ oxides on III–V semiconductors are listed in Table 9.4. Most of these high-κ oxides deposited on III–V semiconductors have a large enough (>1 eV) conduction band offset for MOSFET applications.

Table 9.3

Experimental bandgap energy (E_g), dielectric constant (κ), electron affinity (EA), and optical dielectric constants () of various high-κ oxides along with the calculated charge neutrality level energy above the valence band edge (E_CNL) [20–22]

	Eg (eV)	κ	ECNL (eV)	EA (eV)
a-Al2O3	6.3	7.5 [21]	3.2	3	3.2
HfO2	6	25	3.7	2.2	4
ZrO2	5.8	25	3.6	2.4	4.8
Y2O3	5.7	15	2.4	1.84	4.4
La2O3	6.0	30	2.4	1.9	4
Gd2O3	6	10 [22]	2.4	2.5	3.8

Table 9.4

Calculated conduction band offsets (ΔE_c, in eV) of various high-κ oxides on III–V semiconductors [20]

	Al2O3	HfO2	ZrO2	Y2O3	La2O3	Gd2O3
GaP	0.67	0.77	0.73	1.65	1.65	1.2
InP	1.7	1.72	1.64	2.6	2.6	2.1
AlAs	0.97	1.05	1.0	1.9	1.9	1.5
GaAs	1.46	1.52	1.42	2.4	2.4	1.9
InAs	2.38	2.54	2.44	3.4	3.4	2.9
GaSb	1.50	1.58	1.53	2.46	2.46	2.0
InSb	2.08	2.18	2.14	3.06	3.06	2.62
GaN	0.86	1.15	1.08	2.02	2.02	1.57

9.8.2 Atomic Layer Deposition (ALD)

Atomic layer deposition (ALD) is a vapor-phase film growth method used to deposit ultra-thin, uniform, conformal, and pinhole-free films onto a substrate. It was invented in the 1970s for the production of large-area flat-panel displays. Strong interest in ALD by the semiconductor industry began in the mid-1990s stemming from the need for non-native oxides for continuous scaling of Si MOSFET devices. In 2007, Intel successfully integrated an ALD Hf-based high-κ dielectric process into its 45-nm-node mass production technology. In the meantime, efforts to find non-native oxides on GaAs with low interfacial states density have found a solution in UHV deposition of amorphous Ga₂O₃(Gd₂O₃) and single-crystal Gd₂O₃ on GaAs surface. After this breakthrough in material science, both depletion-mode and enhancement-mode GaAs MOSFETs were demonstrated using Ga₂O₃(Gd₂O₃) as a gate dielectric along with an ion implantation process. The investigation of ALD high-κ Al₂O₃ and HfO₂ on GaAs and other III–V materials for the fabrication of III–V-based MOSFETs started in 2001 at Bell Labs. Soon after in 2003, GaAs MOSFETs with ALD Al₂O₃ gate dielectric were successfully demonstrated. Since then, the research of ALD high-κ dielectrics on III–V substrates has been extended to other material systems including In_xGa_1−xAs, InP, InSb, GaSb, and GaN.

1. (a)

   Principles of ALD

    

An ideal ALD process consists of exposing the substrate surface alternatively to different precursors in a cyclic manner. It differs from CVD technique by keeping the precursors strictly separated from each other in the gas phase. As shown in Fig. 9.53, the process of one ALD growth cycle involves exposure of the substrate surface to alternating precursors A and B introduced sequentially without overlapping. In each alternate precursor pulse, the precursor molecules fully react with the surface in a self-limiting fashion that leaves no more than one monolayer (ML) at the surface. This ensures that the chemisorption reaction stops once all of the reactive sites on the substrate have been occupied. This automatic control of the amount of material deposited is a key feature of ALD. After terminating the pulse of precursor A, an inert gas (typically N₂ or Ar) purge follows to remove the excess of unreacted precursor and gaseous by-products. The second precursor B is then introduced following an inert gas purge to complete one reaction cycle. It should be noticed that only in an ideal case is a monolayer of desired material formed per each reaction cycle. In practice, the material thickness is determined by the nature of the precursor-surface interaction and only a fraction of a monolayer is formed. The ALD cycle can be performed multiple times to increase the film thickness.

Fig. 9.53

Schematic representation of an ALD growth cycle leading to the formation of a binary dielectric film using self-limiting surface chemistry. a Precursor A is pulsed and reacts with surface, b excess precursor and reaction by-products are purged with inert carrier gas, c precursor B is pulsed and reacts with surface, and d excess precursor and reaction by-products are purged with inert carrier gas. Above procedures are repeated until the desired material thickness is achieved

Typically, the process of ALD is performed at relatively low temperatures (<350 °C). The temperature range, where thin film growth proceeds by the irreversible and saturating surface control in an ALD mode, is referred to as the ‘ALD-window’. Within this ALD-window, the deposition rate per cycle is a constant independent of the growth temperature. The process outside the ALD-window, however, generally results in non-ALD-type deposition due to precursor condensation or insufficient reactivity at low temperatures, and precursor thermal decomposition or rapid precursor desorption at high temperatures. Thus, it is necessary to carry out each deposition process within the designated ALD-window.

The main advantages of ALD are derived from the self-limiting and sequential deposition process. First, ALD offers an accurate and simple thickness control by utilizing saturating, irreversible reactions where the film thickness can be tailored by the number of growth cycles. Secondly, ALD provides excellent conformality over large and/or complex-shaped substrates of high aspect ratio and three-dimensionally structured materials. This is made possible by self-limiting, irreversible reactions that provide the same amount of material adsorbed on different parts of substrates. Furthermore, due to the self-limiting reaction nature of ALD, there is no need to control the reactant flux homogeneity and the deposition temperature dependence is weak. A wide range of materials can be deposited using ALD, including oxides, metals, and semiconductors, and there is a wide range of properties that these films can exhibit, depending on the application. However, due to its sequential monolayer deposition nature, ALD suffers from slow deposition rates.

1. (b)

   ALD of high-κ dielectrics on III–V surfaces

    

Since 2007, the Si semiconductor industry has adopted ALD to integrate non-native oxides, e.g., HfO₂-based high-κ dielectric, into its IC mass production lines to advance the technology node beyond 45 nm. Next, at the 22 nm node, a three-dimensional fin field-effect transistor (FinFET) structure is developed. In a FinFET, the fin-shaped gate with a high aspect ratio protruding above the bulk surface needs to be covered with a gate oxide of high compositional and thickness uniformity. This is a task tailored for the conformal ALD process. To further improve the device performance with higher speed and reduced power, it is necessary to look toward alternative semiconductors with higher carrier mobility, such as III–V semiconductors.

For non-native oxide deposited on III–V substrate surface using ALD process, the achieved interface state density is primarily decided by the precursor characteristics and surface preparation of the substrate surface. There are some general requirements for a suitable ALD precursor which include: (a) sufficient volatility but no self-decomposition at the deposition temperature (b) adsorption to the surface sites without etching the substrate, and (c) sufficient reactivity toward the second precursor. The metal precursors used in ALD on III–V surfaces can be divided into two groups, inorganic and organometallic. Halides are the most common inorganic precursors used for both CVD and ALD processes. Chlorides, a kind of halides, are reactive, stable at a broad temperature range, and available for many metals including AlCl₃ and HfCl₄. However, the deposited film may suffer from high residual chlorine and hydrogen content. On the other hand, alkyls, such as trimethyl aluminum (TMA), are ideal metalorganic precursors containing a direct metal carbon bond. They are highly volatile and very reactive with water through hydrolysis. Other metal precursors including the chelation of C (β-diketronates), O (cyclopendienyls), and N (amidinates) with alkyls to a metal have also been used. The variety in non-metal reactants is rather less than in metal reactants. Water, due to its high stability and reactivity in a broad temperature range, is the most commonly used oxygen source providing a hydroxyl-terminated surface in metal oxide ALD. Ozone is often used for deposition of oxides from metal precursors having bulky ligands that are not reactive with water. However, due to its strong oxidation power, there are potential concerns regarding undesirable surface oxide formation on the substrate by prolonged ozone exposures.

The other important factor that influences the quality of non-native oxide/III–V interfaces is the pre-cleaning or surface passivation of the substrate before ALD. Unlike the SiO₂/Si material system, the III–V substrates lack a high-quality, natural insulator. Instead, a number of different native surface species including Ga–O bonds, In-O bonds, As–O bonds, and other III–V–O bonds are readily formed on III–V surfaces when exposed to ambient environment. To achieve a low interface state density on III–V surfaces, these oxides must be removed as much as possible before depositing high-κ dielectrics. Currently, a number of ex situ surface treatments of III–V (100) surfaces have been developed. The use of wet chemical treatment by soaking samples in NH₄OH (29%) solution has been found to be effective in removing higher-oxidation states of As and Ga oxides. To prevent re-oxidation of the III–V surface after the etch, the sample can be further protected by monolayers of sulfur using a (NH₄)₂S treatment before loading into the ALD system. The sulfur is then blown off from the III–V surface during the temperature ramp-up in the ALD system. The key to cleaning up As-oxide and providing high-quality III–V/high-κ interfaces is the self-cleaning effect of the ALD process as described in the following section. However, the removal of Ga oxides by the ALD process is incomplete. Further detailed studies examining Al₂O₃ and HfO₂ deposition on GaAs by ALD indicated that the efficiency of surface oxides removal is affected by the ALD precursors used. An ~1 nm interfacial layer containing significant Ga₂O content was observed at the Al₂O₃/III–V interface deposited using TMA/water precursors, while a thicker interfacial layer (~2.5 nm) was observed from the HfO₂ deposition using HfCl₄/water precursors. The enhanced reactivity of Al(CH₃)₃ compared to HfCl₄ is responsible for this difference.

Currently, Al₂O₃, HfO₂, and their alloys constitute the major ALD dielectrics studied on III–V substrates. Other metal oxides including Gd₂O₃, La₂O₃, and Y₂O₃ have also been studied. The best achieved interface state densities (D_it) are between 10¹¹ and low-10^12/cm²eV, which are orders of magnitude higher than that of (Gd₂O₃)Ga₂O₃/GaAs deposited by in situ UHV MBE deposition (~5 × 10^10/cm²eV) and far worse than the ideal SiO₂/Si system (~10⁹–10¹⁰/cm²eV). However, these interface state density values have already been improved significantly to allow the demonstration of inversion-mode MOSFETs on different III–V substrates. To further improve the technology, additional ALD metal oxides need to be developed for gate dielectrics of III–V substrates. Surface passivation methods before ALD require further refinement to achieve the right surface conditions including the formation of particular species of interfacial oxides. Furthermore, to make high-κ dielectric/III–V a manufacturable III–V CMOS technology, it is also necessary to avoid surface and interfacial defect formation in every step of device fabrication.

9.8.3 Oxides Deposition on III–V Substrates

1. (a)

   Substrate surface preparation

    

In the process of fabricating III–V-based MOSFETs, the preparation of a suitable surface condition of the semiconductor substrate for oxide deposition is the most critical step. In the ideal case, the surface of III–V semiconductors is a perfect, flat, and homogeneous surface. In reality, the atomic bonds in the terminated plane are sheared off to become unsatisfied dangling bonds. These dangling bonds are fairly susceptible to chemical reactions with atmospheric gases leading to the formation of moderately thick native oxides and carbonaceous adsorbents. These native surface species including, e.g., Ga–O bonds, As–O bonds, elemental As, and As and Ga anti-sites on GaAs, are the culprits of the Fermi level pinning. Thus, it is very important to remove these native oxides and carbonaceous adsorbents on air-exposed III–V substrates such that further surface treatment or ‘passivation’ of the surface can be carried out before the deposition of high-κ dielectrics.

On the other hand, under the UHV conditions, in a clean surface without atmospheric gas contamination, those unpaired electrons of dangling bonds tend to form covalent bonds between adjacent atoms in a process termed ‘dimerization.’ These surface dimmers have a tendency to form highly ordered rows in order to minimize the free energy of the surface. Using reflection high-energy electron diffraction (RHEED) technique, the observed reconstructed surface structures of GaAs vary from Ga-rich (4 × 2) reconstruction through As-rich (2 × 4) reconstruction depending on the substrate temperature and the As-to-Ga beam flux ratio. The As-rich (2 × 4) surface is terminated with As dimers aligned along the [10] direction, while the Ga-rich (4 × 2) surface has Ga dimers aligned along the [] direction. Due to the high diffusivity of surface Ga atoms, prolonged exposure of the GaAs surface under high temperature and low As flux promotes the island formation leading to uneven morphology on Ga-rich GaAs surface. In contrast, the As-rich (2 × 4) surface, obtained under medium (~550 to 600 °C) temperature and As-beam flux conditions, provides a smooth surface. Since the FETs are surface devices, for in situ deposition of oxides under UHV conditions, the As-rich (2 × 4) surface is the one most relevant for MOSFET applications.

1. (b)

   Surface passivation and oxide deposition

    

Over the past five decades, persistent efforts have been carried out in searching for surface treatment methods to passivate III–V surfaces such that MOSFETs can be demonstrated. However, the conventional practice of thermal, anodic, and plasma oxidation methods failed to achieve this goal. Using an in situ deposition approach, the first successful passivation of GaAs surface was demonstrated in 1995 by Minghwei Hong et al. at Bell Labs [23]. In this method, electron-beam evaporated Ga₂O₃(Gd₂O₃) [GGO] dielectric film was deposited on an MBE-grown wafer in a UHV connected multiple chamber system. During the experiment, the freshly grown GaAs with an As-stabilized (2 × 4) surface was transferred under UHV condition from the III–V MBE chamber to another chamber for oxide deposition. Prior to deposition, the GaAs surface stoichiometry and atomic order were preserved, as monitored using RHEED, with extremely low oxygen exposure. Then the GGO film was deposited on the clean, atomically ordered (100) GaAs surface at substrate temperatures below 600 °C to avoid chemical reactions with GaAs substrates. The oxide molecules were supplied by electron-beam evaporation of a single-crystal Gd₃Ga₅O₁₂ source. MOS structures on GaAs with a low D_it on the order of mid 10¹⁰ cm⁻² eV⁻¹ were demonstrated for the first time. However, low D_it values were not obtained in other oxide/GaAs systems using Al₂O₃, SiO₂, and MgO prepared by a similar approach. Furthermore, pure Ga₂O₃ films cannot passivate GaAs surfaces effectively and show very high leakage current with poorly defined breakdown characteristics.

Further studies indicated that the unpinning of the GaAs Fermi level using electron-beam evaporated GGO dielectric film results from the Gd₂O₃ epilayer restoring the surface As and Ga atoms to near-bulk charge. An understanding of the bonding between Gd₂O₃ and GaAs is important for the development of new dielectrics used in III–V-based MOSFETs. Based on the consideration of Gibbs free energies of formation of all possible pairs in Ga, As, Gd, and O, the growth initiates from bonding a layer of oxygen atoms to Ga (Ga₂O₃: −998 kJ/mole) by taking up the As site (GaAs: −70 kJ/mole) in GaAs structure. Then the oxygen atoms would proceed to bind to Gd atoms of the next row due to the very large Gibbs energy for Gd₂O₃ formation (−1739 kJ/mole). Thus, the initial growth of GGO on GaAs contains only Gd₂O₃, despite the fact that incoming fluxes consist of various other species including Ga₂O₃. In addition, this Gd₂O₃ film is grown in a single-crystal form on GaAs. The Gd₂O₃ film has a cubic structure isomorphic to Mn₂O₃ and is (110)-oriented in single domain on the (100) GaAs surface. Once a Gd₂O₃/GaAs interface is formed, however, the competition for oxygen is significantly reduced and inclusion of Ga₂O₃ becomes possible, resulting in an oxide mixture of Gd₂O₃ and Ga₂O₃. Thus, the high interface quality GGO/GaAs heterostructure consists of a transition from a single-crystal GaAs substrate, to an epitaxial coherent Gd₂O₃ oxide layer of two to three monolayers in thickness, and then to the amorphous mixed oxides. This result matches well with the model of high-quality SiO₂/Si interface, where the crystalline-Si to amorphous-SiO₂ transformation takes place via an ordered crystalline oxide layer ~5 Å thick. The in situ UHV deposition of Gd₂O₃ approach can be extended to other rare earth oxides due to their chemical similarity. For example, using Y₂O₃ as the high-κ dielectric, low trap densities of (3 − 5) × 10¹¹ eV⁻¹cm⁻² have been achieved at the Y₂O₃/GaAs (001) interface. Similar to Gd₂O₃, the Y₂O₃ film is also grown in a single-crystal form on GaAs with Y₂O₃ (110) planes parallel to GaAs (001) planes.

In contrast to the in situ deposition approach, MOSFETs were also successfully demonstrated in 2003 using ex situ ALD high-κ Al₂O₃ films as the gate dielectrics on GaAs and other III–V materials. Metalorganic trimethyl aluminum and water were used as the metal precursor and oxygen source for the ALD process, respectively. Since the ALD process was conducted on the GaAs surface exposed to the ambient air after epitaxial growth, a thin native oxide layer consisting of Ga and As oxides as well as spurious organic contamination is formed on the GaAs surface. To achieve a low interface state density on III–V surfaces, these oxides must be removed as much as possible before depositing high-κ dielectrics. Currently, a number of ex situ surface treatments of III–V (100) surfaces using a combination of wet chemical etch in NH₄OH (29%) solution and (NH₄)₂S treatment before loading into the ALD system have been developed as outlined in the previous section. The self-cleaning effect of the ALD process further cleans up the As-oxide and provides high-quality III–V/high-κ interfaces. For selected ALD precursors, the detailed process parameters are mainly decided by the precursor characteristics such as decomposition behavior, sticking coefficient, vapor pressure, etc. So far, a number of suitable metal precursors have been reported for ALD deposition of high-κ dielectrics on various III–V surfaces with Al₂O₃, HfO₂, and their alloys constitute the most studied systems.

To understand interface passivation on III–V surfaces by ALD requires the knowledge of the surface oxides likely to be present on the surface in the course of device fabrication. In situ film deposition and analysis of the chemical state of the oxide interface can give a clear picture of the detailed reactions. An example of interface reactions of Al₂O₃ and HfO₂ ALD processes on the NH₄OH-treated GaAs surface using in situ X-ray photoelectron spectroscopy (XPS) is shown in Fig. 9.54. The air-exposed starting material is covered with native Ga and As oxides and excess As. The As 2p spectra show two As oxidation states, As³⁺ and As⁵⁺, corresponding to As₂O₃ and As₂O₅, respectively. The Ga–O signal of the Ga 2p spectra has multiple oxidation states including Ga³⁺ and Ga⁵⁺ as well as other oxide species. It is noted that the weaker bonded, higher-oxidation As states, e.g., As₂O₅ or As⁵⁺ states, are removed completely by wet NH₄OH-treatment, leaving behind As³⁺ oxidation As states, reduced GaO_x species as well as As–As bonding. The reduction of the As³⁺ oxidation state occurs during the TMA precursor pulse, whereby the Al³⁺ in the TMA precursor more efficiently replaces the As in the As³⁺ oxidation state, resulting in AlO_x formation and presumably volatile As(CH₃)₃ reaction products. However, the reaction with As³⁺ oxidation state is less efficient for Hf originating from the tetrakis (ethylmethylamino) hafnium (TEMA-Hf) precursor. It is also noted that As–As bonding and GaO_x oxidation states persist throughout the growth process in both Al₂O₃ and HfO₂ ALD samples. These detectable residual surface oxides at the interface result in a considerable interface state density D_it ≥ 2 × 10¹² cm⁻² eV⁻¹. In contrast, the interface state density achieved for in situ deposited GGO grown by MBE on GaAs is as low as D_it ~ 5 × 10¹⁰ cm⁻² eV⁻¹.

Fig. 9.54

As 2p and Ga 2p X-ray photoelectron spectroscopy (XPS) spectra of a native oxides on GaAs, and interface reactions after b NH₄OH-treatment of GaAs, c additional Al₂O₃ ALD process, and d additional HfO₂ ALD process. A substantial reduction of the As- and Ga-oxides is noted. Reprinted with permission from [24], copyright AIP Publishing

As shown in Fig. 9.54, the presence of surface defects such as As-As dimers and AsO_x persists in ex situ ALD fabricated high-κ dielectric/III–V semiconductor structures, and has been speculated to be the cause for the high D_it’s, or D_it peaks in the mid-bandgap of III–V materials. These defects mainly originate from the native oxide layer formed during the exposure of semiconductors to the ambient environment in ALD. To improve the high-κ dielectric/III–V semiconductor interface quality, one approach is to combine ALD with in situ UHV deposition, or in situ ALD process, such that the surface exposure to ambient is completely avoided during ALD processes. Direct comparisons between in situ and ex situ deposited ALD-Al₂O₃ on In_0.53Ga_0.47As have revealed that the in situ method shows no detectable AsO_x component at the dielectric–semiconductor interface, whereas some AsO_x residue is detected using the ex situ approach. A reduction of D_it by more than half is observed for the in situ method. Furthermore, as detailed in the following section, the fabricated inversion-channel In_0.53Ga_0.47As MOSFETs show much improved device performances for the in situ method than the ex situ method. The intrinsic drain current (I_d), transconductance (g_m), and effective mobility (µ_eff) are all improved by more than threefold over that of the ex situ method. In_0.53Ga_0.47As MOSFETs with similar performances have also been achieved using in situ ALD HfO₂ and UHV-Y₂O₃ as gate dielectrics. Similar improvements of D_it using in situ ALD of Al₂O₃, HfO₂, and Y₂O₃ on GaAs have also been demonstrated. A low interface trap density D_it of ~2 × 10¹¹ cm⁻² eV⁻¹ has been achieved in in situ ALD Y₂O₃ and HfO₂ on n-GaAs(001) and p-GaAs(001), respectively. The low interface trap density is key to the high performances of III–V-based MOSFETs.

9.8.4 High-κ Dielectric/III–V MOSFET Development

Using in situ deposition, and in situ and ex situ ALD approaches, various high-κ/III–V inversion-mode MOSFETs using GaAs, InGaAs, and GaN as channel materials have been demonstrated. Among them, the In_0.53Ga_0.47As MOSFET is the most extensive studied due to its high electron mobility, high saturation velocity, and smaller charge neutrality level below the conduction band minimum of the channel material. Figure 9.55 benchmarks performances of state-of-the-art In_0.53Ga_0.47As enhancement-mode planar and non-planar MOSFETs incorporated with various high-κ dielectrics. The non-planar structures include tri-gate, multigate, and gate-all-around (GAA) devices. The UHV deposited GGO and Y₂O₃, in situ ALD HfO₂ and Al₂O₃, and ex situ ALD Al₂O₃ are used as the gate dielectrics. The drain currents for all devices are compared at the same bias conditions of V_DS = 1 V and V_GS − V_T = 1 V. The general trend is that the 1-µm gate length MOSFETs using in situ high-κ dielectrics show better I_DS and maximum g_m compared to smaller gate length devices with ex situ high-κ dielectrics, even though the bias conditions are not favorable for 1-µm gate length MOSFETs. The 1-µm gate length In_0.53Ga_0.47As MOSFETs with in situ ALD-Al₂O₃ dielectrics show superb I_DS of 0.72 mA/µm, which compares favorably with other planar and non-planar InGaAs MOSFETs with ex situ ALD-Al₂O₃ dielectrics and significantly smaller gate lengths. The in situ ALD-Al₂O₃ MOSFETs also have the best maximum g_m of 0.98 mS/µm at V_DS = 2 V. Other MOSFETs with UHV deposited GGO and Y₂O₃, and in situ ALD HfO₂ high-κ dielectrics, also show excellent I_DS and maximum g_m. The low interface trap density associated with in situ high-κ dielectrics is key to the high performances of these devices.

Fig. 9.55

Benchmark of a drain current at V_DS = V_GS − V_T = 1 V and b peak transconductance of in situ high-κ dielectrics/In_0.53Ga_0.47As MOSFETs and other enhancement-mode planar and non-planar devices using ex situ (solid symbols) high-κ dielectrics.

Reprinted with permission from [25], copyright AIP Publishing

During the past two decades, tremendous progress has been made in realizing both enhancement-mode and depletion-mode high-κ dielectrics/III–V MOSFETs. However, there exist several difficult challenges to overcome before III–V materials become appropriate for future high-speed, low-power logic applications. First, for III–V MOSFETs to be competitive against scaled Si MOSFETs, their physical gate length needs to be scaled to 30 nm and below with acceptable I_ON/I_OFF ratio (>10⁴) at V_CC = 0.5 V. Recent demonstration of high-performance devices described above has already laid a solid foundation in achieving this goal. Second, for CMOS logic applications, there is a need for p-channel MOSFETs with very high hole mobility. Although III–V materials show 10–20 times better electron mobility compared to Si, their hole mobility is comparable to that of Si. To improve the hole mobility in III–V materials, one approach is to use compressively strained III–V channels in MOSFETs. Alternatively, other novel materials exhibiting high hole mobility, e.g., strained Ge quantum wells, can be used as the p-channel materials. Finally, to take advantage of the advanced development of Si IC technologies and the high-speed, low-power capabilities of III–V devices, it is desirable to monolithically integrate III–V devices selectively onto the Si platform. To achieve this goal, one has to solve two significant challenges, namely the lattice-mismatch and thermal mismatch between Si and III–V’s.

Problems

1. 1.

   Refer to the experimental results of an Al_0.3Ga_0.7As/GaAs HEMT reported in [6].

   1. (a)

      Estimate the threshold voltage V_T for three samples (R-96A, R-73A, and R-72A).

       
   2. (b)

      The 2DEG in the triangular quantum well has a sine-wave-like distribution perpendicular to the conduction channel. What is the average concentration peak of the 2DEG located ΔW away from the heterojunction interface? The results can be calculated using the equation

      

      Assume V_DS = 0 and comment on your results in terms of whether they are realistic.

       
   3. (c)

      Estimate ΔW again using Howard–Fang approximation for the triangular QW at the interface. Also discuss your results.

       
    

1. 2.

   In an Al_0.2Ga_0.8As/Ga_0.85In_0.15As pseudomorphic high-electron-mobility transistor (pHEMT), the Al_0.2Ga_0.8As barrier is uniformly doped at a level of 2 × 10¹⁸ cm⁻³. At the Al_0.2Ga_0.8As/Ga_0.85In_0.15As interface, there is an undoped spacer layer on the Al_0.2Ga_0.8As side.

   1. (a)

      Calculate the sheet carrier concentration in the triangular Ga_0.85In_0.15As quantum well for different spacer layer thickness (W_sp) of 25 Å and 100 Å. Assume the donor level in Al_0.2Ga_0.8As is sufficiently deep (E_d = 50 meV) so that the Fermi level is pinned there. The dielectric constant of Ga_0.85In_0.15As is 13.41ε₀.

       
   2. (b)

      Plot the equilibrium energy band diagram of the whole pHEMT structure, including metal contact, for the W_sp = 25 Å case using SimWindows. Assume the total Al_0.2Ga_0.8As barrier has a thickness of 150 Å and the undoped Ga_0.85In_0.15As 2DEG channel is 100 Å thick. The whole structure is grown on top of an undoped GaAs substrate. The metal-Al_0.2Ga_0.8As work function qϕ_m equals ~0.9 eV.

       
   3. (c)

      Repeat part (a) for a modulation-doped Al_0.3Ga_0.7As/GaAs heterostructure with a 25 Å spacer layer and ΔE_c = 0.2 eV. This HEMT structure has the same doping level in the Al_0.3Ga_0.7As barrier. The dielectric constant of GaAs is 12.85.

       
   4. (d)

      Now the 2DEG channel material of the pHEMT is replaced with a GaAs_0.8Sb_0.2 layer, but keep all other materials unchanged. For W_sp = 25 Å, calculate the sheet carrier concentration in the triangular GaAsSb QW. Will this material system outperform the Al_0.2Ga_0.8As/Ga_0.85In_0.15As pHEMT structure? Why?

       
    

The relevant material parameters are listed below:

For Ga_0.85In_0.15As:  = 0.025(1 − x) + 0.71x − 0.0163x(1 − x)

For GaAs_0.8Sb_0.2:  = 0.00634 − 0.0483x − 0.0252x².

1. 3.

   The 2DEG with a sheet carrier density of 10¹³ cm⁻² is obtained at the interface of an Al_xGa_1−xN/GaN HEMT structure grown by MOCVD. The Al_xGa_1−xN barrier is undoped and has a thickness of 30 nm. Using parameters provided in the reference article [9], verify that the Al-composition (x) of the Al_xGa_1−xN barrier is about 0.2 as shown in Fig. 11 of the referenced article.

    
2. 4.

   Repeat Problem 3 with up-to-date material parameters of Al_xGa_1−xN shown below:

    

ΔE_c(x) ≈ 2.12x,

E_g(x) = xE_g(AlN) + (1–x)E_g(GaN) − 0.7x(1–x).

Dielectric constant (x) = 9.5 − x,

m*(x) = 0.22m_e,

qϕ_m(x) = 1.3x + 0.84 (eV).

Assuming the Al-composition of the Al_xGa_1−xN barrier in the Al_xGa_1−xN/GaN HEMT is x = 0.2, calculate the 2DEG sheet carrier density at the Al_xGa_1−-xN/GaN interface.

1. 5.
   The active region of a p-channel pseudomorphic high-hole-mobility transistor (pHHMT) has a compressively strained InSb channel material and an Al_0.35In_0.65Sb barrier. For a 5 nm InSb QW sandwiched between Al_0.35In_0.65Sb barrier, the type-I band discontinuities, ΔE_c and ΔE_v, are determined as 0.342 and 0.254 eV, respectively. Assume the 200 Å thick Al_0.35In_0.65Sb barrier consists of a uniformly Be-doped layer of p = 10¹⁸ cm⁻³ and an undoped spacer layer, W_sp = 70 Å.

   1. (a)

      Calculate the sheet carrier concentration in the triangular InSb quantum well. Assume the acceptor level in Al_0.35In_0.65Sb is sufficiently deep (E_a = 40 meV) so that the Fermi level is pinned there.

       
   2. (b)

      Plot the equilibrium energy band diagram of the whole pHHMT structure, including metal contact, using SimWindows. The plot should extend into the AlInSb buffer layer for 200 Å. Assume the metal-Al_0.35In_0.65Sb work function qϕ_m equals ~0.16 eV.

       
    
2. 6.

   In pursuing high-speed HBTs, InP-based material systems are the most promising. One of the systems being actively studied is based on using GaSb_0.5As_0.5 lattice-matched to InP as the base material.

   1. (a)

      Find the band discontinuity values between lattice-matched GaSb_0.5As_0.5 and InP. Is this a type-I or type-II heterojunction?

       
   2. (b)

      In Ga_0.47In_0.53As/InP N-p-N DHBTs, the valence band discontinuity between InP emitter and Ga_0.47In_0.53As base is 0.36 eV. The ΔE_c in this type-I heterojunction is 0.252 eV. By replacing the Ga_0.47In_0.53As with lattice-matched GaSb_0.5As_0.5, the maximum current gain can be improved. Calculate the maximum current gain improvement.

       
   3. (c)

      Compare the properties of GaSb_0.5As_0.5/InP and Ga_0.47In_0.53As/InP HBTs.

       
    
3. 7.

   Ga_xIn_1−xP is a useful material for visible light-emitting and HBT applications.

   1. (a)

      Calculate the composition x and band gap energy of Ga_xIn_1−xP lattice-matched to GaAs.

       
   2. (b)

      Using model-solid theory, calculate the band discontinuities between lattice-matched Ga_xIn_1−xP and GaAs.

       
   3. (c)

      In Al_0.3Ga_0.7As/GaAs HBTs, the valence band discontinuity between Al_0.3Ga_0.7As emitter and GaAs base is 0.132 eV. By replacing the Al_0.3Ga_0.7As with lattice-matched Ga_xIn_1−xP the maximum current gain can be improved. Calculate the magnitude of current gain improvement.

       
   4. (d)

      Does Ga_xIn_1−xP offer any advantages over Al_0.3Ga_0.7As as the barrier layer in an Ga_xIn_1−xP/GaAs high-electron mobility transistor? Why? Note, the conduction band discontinuity in the Al_0.3Ga_0.7As/GaAs system is 0.263 eV.

       
    
4. 8.

   Mini project: During the last 60 years, the density and feature size of Si ICs have followed Moore’s law faithfully through device scaling. However, the current Si technology will hit a feature size limit in the near future. New channel materials for increased electron and hole mobility, well above those achievable in strained Si, are needed. As gate dielectric scaling becomes increasingly difficult, carrier transport enhancement will become essential for current enhancement in the advanced FETs of future CMOS generations. One of the major problems encountered in developing FETs based on materials other than Si is the large disparity between electron and hole mobility. In order to design complementary FETs (i.e., one n-channel and one p-channel, and not limited to MOSFET), a material system with high hole mobility is required.

    

In this problem, the goal is to design a p-channel quantum well FET (QWFET) similar to the high-hole-mobility QWFET reported by Intel in 2008. (M. Radosavljevic et al., 2008 IEEE IEDM Tech. Dig., https://​doi.​org/​10.​1109/​iedm.​2008.​4796798)

Your work should meet the following requirements:

• Select a material system among all available III–V materials for high hole mobility. Explain why you select it. However, you cannot copy the structure reported by Intel. Recall that in Chap. 6, we learned that under compressive strain, the heavy-hole band is lifted above the light-hole band in the growth direction (perpendicular to surface). But in the direction parallel to the surface (perpendicular to the growth direction), the effective mass becomes lighter. (See S. L. Chuang, Phys. Rev., B43, 9649, 1991.)

• The selected material system should be able to form QWFET structures with high crystal quality. Of course, high-quality heterostructures prepared on metamorphic substrate structures are allowed. (That means you can use materials with any lattice constant as the substrate).

• Design the layer structure of a QWFET based on the material system selected. We restrict the selection of FET structure to QWFETs (including pseudomorphic structures). Provide detailed material and device parameters such as ΔE_v, N_S and layer structures along with full energy band diagram. For heterostructures, the energy band discontinuities should be calculated. The portion of gate contact should also be included.

• To simplify the calculation, set the spacer layer thickness as W_sp = 25 Å and the acceptor level in the barrier layer as E_a = 40 meV. The Schottky barrier height of the barrier layer can be determined following the method reported by Tiwari and Frank (Appl. Phys. Lett., 60, 630, 1992).

• Your final device layer structure should be a depletion mode FET at zero gate bias.

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Further Reading

1. 1.
   C. Weisbuch, B. Vinter, Quantum Semiconductor Structures (Academic Press, 1991)
2. 2.
   J.H. Davies, The Physics of Low-Dimensional Semiconductors (Cambridge, 1998)
3. 3.
   B.G. Streetman, S. Banerjee, Solid State Electronic Devices, 6th edn. (Prentice-Hall, 2006)
4. 4.
   S.M. Sze, High-Speed Semiconductor Devices (Wiley, 1990)
5. 5.
   C.W. Wilmsen (ed.), Physics and Chemistry of III–V Compound Semiconductor Interfaces (Plenum Press, New York, 1985)
6. 6.
   S. Oktyabrsky, P.D. Ye (eds.), Fundamentals of III-V Semiconductor MOSFETs (Springer, New York, 2010)
7. 7.
   S.M. George, Chem. Rev. 110, 111 (2010)Crossref