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Index
Half title page
Title page
Copyright page
Contents
Preface to the first edition
Preface to the second edition
Physical constants and unit conversions
List of symbols
1 Introduction
1.1 Evolution of VLSI Device Technology
1.1.1 Historical Perspective
1.1.2 Recent Developments
1.2 Modern VLSI Devices
1.2.1 Modern CMOS Transistors
1.2.2 Modern Bipolar Transistors
1.3 Scope and Brief Description of the Book
2 Basic Device Physics
2.1 Electrons and Holes in Silicon
2.1.1 Energy Bands in Silicon
2.1.2 n-Type and p-Type Silicon
2.1.3 Carrier Transport in Silicon
2.1.4 Basic Equations for Device Operation
2.2 p-n Junctions
2.2.1 Energy-Band Diagrams for a p–n Diode
2.2.2 Abrupt Junctions
2.2.3 The Diode Equation
2.2.4 Current–Voltage Characteristics
2.2.5 Time-Dependent and Switching Characteristics
2.2.6 Diffusion Capacitance
2.3 MOS Capacitors
2.3.1 Surface Potential: Accumulation, Depletion, and Inversion
2.3.2 Electrostatic Potential and Charge Distribution in Silicon
2.3.3 Capacitances in an MOS Structure
2.3.4 Polysilicon-Gate Work Function and Depletion Effects
2.3.5 MOS under Nonequilibrium and Gated Diodes
2.3.6 Charge in Silicon Dioxide and at the Silicon–Oxide Interface
2.3.7 Effect of Interface Traps and Oxide Charge on Device Characteristics
2.4 Metal–Silicon Contacts
2.4.1 Static Characteristics of a Schottky Barrier Diode
2.4.2 Current Transport in a Schottky Barrier Diode
2.4.3 Current–Voltage Characteristics of a Schottky Barrier Diode
2.4.4 Ohmic Contacts
2.5 High-Field Effects
2.5.1 Impact Ionization and Avalanche Breakdown
2.5.2 Band-to-Band Tunneling
2.5.3 Tunneling into and through Silicon Dioxide
2.5.4 Injection of Hot Carriers from Silicon into Silicon Dioxide
2.5.5 High-Field Effects in Gated Diodes
2.5.6 Dielectric Breakdown
Exercises
3 MOSFET Devices
3.1 Long-Channel MOSFETs
3.1.1 Drain-Current Model
3.1.2 MOSFET I–V Characteristics
3.1.3 Subthreshold Characteristics
3.1.4 Substrate Bias and Temperature Dependence of Threshold Voltage
3.1.5 MOSFET Channel Mobility
3.1.6 MOSFET Capacitances and Inversion-Layer Capacitance Effect
3.2 Short-Channel MOSFETs
3.2.1 Short-Channel Effect
3.2.2 Velocity Saturation and High-Field Transport
3.2.3 Channel Length Modulation
3.2.4 Source–Drain Series Resistance
3.2.5 MOSFET Degradation and Breakdown at High Fields
Exercises
4 CMOS Device Design
4.1 MOSFET Scaling
4.1.1 Constant-Field Scaling
4.1.2 Generalized Scaling
4.1.3 Nonscaling Effects
4.2 Threshold Voltage
4.2.1 Threshold-Voltage Requirement
4.2.2 Channel Profile Design
4.2.3 Nonuniform Doping
4.2.4 Quantum Effect on Threshold Voltage
4.2.5 Discrete Dopant Effects on Threshold Voltage
4.3 MOSFET Channel Length
4.3.1 Various Definitions of Channel Length
4.3.2 Extraction of the Effective Channel Length
4.3.3 Physical Meaning of Effective Channel Length
4.3.4 Extraction of Channel Length by C–V Measurements
Exercises
5 CMOS Performance Factors
5.1 Basic CMOS Circuit Elements
5.1.1 CMOS Inverters
5.1.2 CMOS NAND and NOR Gates
5.1.3 Inverter and NAND Layouts
5.2 Parasitic Elements
5.2.1 Source–Drain Resistance
5.2.2 Parasitic Capacitances
5.2.3 Gate Resistance
5.2.4 Interconnect R and C
5.3 Sensitivity of CMOS Delay to Device Parameters
5.3.1 Propagation Delay and Delay Equation
5.3.2 Delay Sensitivity to Channel Width, Length, and Gate Oxide Thickness
5.3.3 Sensitivity of Delay to Power-Supply Voltage and Threshold Voltage
5.3.4 Sensitivity of Delay to Parasitic Resistance and Capacitance
5.3.5 Delay of Two-Way NAND and Body Effect
5.4 Performance Factors of Advanced CMOS Devices
5.4.1 MOSFETs in RF Circuits
5.4.2 Effect of Transport Parameters on CMOS Performance
5.4.3 Low-Temperature CMOS
Exercises
6 Bipolar Devices
6.1 n–p–n Transistors
6.1.1 Basic Operation of a Bipolar Transistor
6.1.2 Modifying the Simple Diode Theory for Describing Bipolar Transistors
6.2 Ideal Current–Voltage Characteristics
6.2.1 Collector Current
6.2.2 Base Current
6.2.3 Current Gains
6.2.4 Ideal IC–VCE Characteristics
6.3 Characteristics of a Typical n–p–n Transistor
6.3.1 Effect of Emitter and Base Series Resistances
6.3.2 Effect of Base–Collector Voltage on Collector Current
6.3.3 Collector Current Falloff at High Currents
6.3.4 Nonideal Base Current at Low Currents
6.4 Bipolar Device Models for Circuit and Time-Dependent Analyses
6.4.1 Basic dc Model
6.4.2 Basic ac Model
6.4.3 Small-Signal Equivalent-Circuit Model
6.4.4 Emitter Diffusion Capacitance
6.4.5 Charge-Control Analysis
6.5 Breakdown Voltages
6.5.1 Common-Base Current Gain in the Presence of Base–Collector Junction Avalanche
6.5.2 Saturation Currents in a Transistor
6.5.3 Relation Between BVCEO and BVCBO
Exercises
7 Bipolar Device Design
7.1 Design of the Emitter Region
7.1.1 Diffused or Implanted-and-Diffused Emitter
7.1.2 Polysilicon Emitter
7.2 Design of the Base Region
7.2.1 Relationship between Base Sheet Resistivity and Collector Current Density
7.2.2 Intrinsic-Base Dopant Distribution
7.2.3 Electric Field in the Quasineutral Intrinsic Base
7.2.4 Base Transit Time
7.3 Design of the Collector Region
7.3.1 Collector Design When There Is Negligible Base Widening
7.3.2 Collector Design When There Is Appreciable Base Widening
7.4 SiGe-Base Bipolar Transistors
7.4.1 Transistors Having a Simple Linearly Graded Base Bandgap
7.4.2 Base Current When Ge Is Present in the Emitter
7.4.3 Transistors Having a Trapezoidal Ge Distribution in the Base
7.4.4 Transistors Having a Constant Ge Distribution in the Base
7.4.5 Effect of Emitter Depth Variation on Device Characteristics
7.4.6 Some Optimal Ge Profiles
7.4.7 Base-Width Modulation by VBE
7.4.8 Reverse–Mode I–V Characteristics
7.4.9 Heterojunction Nature of a SiGe-Base Bipolar Transistor
7.5 Modern Bipolar Transistor Structures
7.5.1 Deep-Trench Isolation
7.5.2 Polysilicon Emitter
7.5.3 Self-Aligned Polysilicon Base Contact
7.5.4 Pedestal Collector
7.5.5 SiGe-Base
Exercises
8 Bipolar Performance Factors
8.1 Figures of Merit of a Bipolar Transistor
8.1.1 Cutoff Frequency
8.1.2 Maximum Oscillation Frequency
8.1.3 Ring Oscillator and Gate Delay
8.2 Digital Bipolar Circuits
8.2.1 Delay Components of a Logic Gate
8.2.2 Device Structure and Layout for Digital Circuits
8.3 Bipolar Device Optimization for Digital Circuits
8.3.1 Design Points for a Digital Circuit
8.3.2 Device Optimization When There Is Significant Base Widening
8.3.3 Device Optimization When There Is Negligible Base Widening
8.3.4 Device Optimization for Small Power–Delay Product
8.3.5 Bipolar Device Optimization from Some Data Analyses
8.4 Bipolar Device Scaling for ECL Circuits
8.4.1 Device Scaling Rules
8.4.2 Limits in Bipolar Device Scaling for ECL Circuits
8.5 Bipolar Device Optimization and Scaling for RF and Analog Circuits
8.5.1 The Single-Transistor Amplifier
8.5.2 Optimizing the Individual Parameters
8.5.3 Technology for RF and Analog Bipolar Devices
8.5.4 Limits in Scaling Bipolar Transistors for RF and Analog Applications
8.6 Comparing a SiGe-Base Bipolar Transistor with a GaAs HBT
Exercises
9 Memory Devices
9.1 Static Random-Access Memory
9.1.1 CMOS SRAM Cell
9.1.2 Other Bistable MOSFET SRAM Cells
9.1.3 Bipolar SRAM Cell
9.2 Dynamic Random-Access Memory
9.2.1 Basic DRAM Cell and Its Operation
9.2.2 Device Design and Scaling Considerations for a DRAM Cell
9.3 Nonvolatile Memory
9.3.1 MOSFET Nonvolatile Memory Devices
9.3.2 Flash Memory Arrays
9.3.3 Floating-Gate Nonvolatile Memory Cells
9.3.4 Nonvolatile Memory Cells with Charge Stored in Insulator
Exercise
10 Silicon-on-Insulator Devices
10.1 SOI CMOS
10.1.1 Partially Depleted SOI MOSFETs
10.1.2 Fully Depleted SOI MOSFETs
10.2 Thin-Silicon SOI Bipolar
10.2.1 Fully Depleted Collector Mode
10.2.2 Partially Depleted Collector Mode
10.2.3 Accumulation Collector Mode
10.2.4 Discussion
10.3 Double-Gate MOSFETs
10.3.1 An Analytic Drain Current Model for Symmetric DG MOSFETs
10.3.2 The Scale Length of Double-Gate MOSFETs
10.3.3 Fabrication Requirements and Challenges of DG MOSFETs
10.3.4 Multiple-Gate MOSFETs
Exercise
Appendix 1 CMOS Process Flow
Appendix 2 Outline of a Process for Fabricating Modern n–p–n Bipolar Transistors
Appendix 3 Einstein Relations
Appendix 4 Spatial Variation of Quasi-Fermi Potentials
Appendix 5 Generation and Recombination Processes and Space-Charge-Region Current
Appendix 6 Diffusion Capacitance of a p–n Diode
Appendix 7 Image-Force-Induced Barrier Lowering
Appendix 8 Electron-Initiated and Hole-Initiated Avalanche Breakdown
Appendix 9 An Analytical Solution for the Short-Channel Effect in Subthreshold
Appendix 10 Generalized MOSFET Scale Length Model
Appendix 11 Drain Current Model of a Ballistic MOSFET
Appendix 12 Quantum-Mechanical Solution in Weak Inversion
Appendix 13 Power Gain of a Two-Port Network
Appendix 14 Unity-Gain Frequencies of a MOSFET Transistor
Appendix 15 Determination of Emitter and Base Series Resistances
Appendix 16 Intrinsic-Base Resistance
Appendix 17 Energy-Band Diagram of a Si–SiGe n–p Diode
Appendix 18 fT and fmax of a Bipolar Transistor
References
Index
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