Make · FPGAs by Romano, David -- Read -- Imperial Library of Trantor

Index

Preface

FPGA History About the Book Conventions Used in This Book Using Code Examples Safari® Books Online How to Contact Us Acknowledgments

1. Overview

Papilio Opal Kelly Red Pitaya Numato Lab Design Flow

Concept Phase Design Phase Test Phase Synthesize Phase Build Phase Run Phase

Takeaways

2. Count on It!

Blink LEDs Concept

How It Works Xilinx ISE WebPACK Installation

Getting started Installation

Design

Peripheral Breadboard FPGA Circuit Schematic Design Entry FPGA Circuit HDL Design Entry Simulation Build

Assigning Physical I/O Creating the Constraints File Bit File Generation

Program Target Device

Open Kelly Setup

Setup Test

Clock Frequency Experimentation Takeaways

3. That’s Refreshing

Stopwatch Concept

How It Works

Design

Peripheral Breadboard

BoM

FPGA Circuit Digital Clock Manager (DCM) Verilog Code and Concurrency

Simulation Build

Assigning Physical I/O

Takeaways

4. Testing 1, 2, 3, 4

The Test Bench

Test Bench Anatomy

Reuse Running the Test Bench Project

Step 1: Selection and Download of Core Step 2: Documentation Step 3: RTL Step 4: Adding Test Bench Files and Running the Simulation

Exploring the Test Bench Project

Overview

Code Walk

Timescale and delays Instantiating the DUT and generators Clocks and resets Display Tasks Waves

Stepping

Takeaways

5. It Does Not Compute

The CARDIAC Computer Model Getting Started with VTACH

Numato Elbert V2 Setup

Modifications

Step 1: Device Section Step 2: Pin Assignments

7-Segment Display

Step 3: Clocking Step 4: I/O Polarity Step 5: Memory Block Update

Design, Build, and Simulation

Simulation

Building and Running Programing and Assembler Takeaways

6. It’s a Small World!

System on Chip SoC Architecture DesignLab

Installation

Papilio DUO Setup

Step 1: Power Up Step 2: Select COM Port Step 3: Create Project Step 4: Associate Circuit Step 5: Load FPGA Bit File Step 6: Compile and Upload Sketch

Getting Started with the DesignLab Video-Audio Player

How It Works

Design

Step 1: Create New DesignLab Project Step 2: Edit Your Design in Xilinx ISE Step 3: Add VGA Adapter Block Step 4: Add Audio Blocks Step 5: Implement and Generate Bit File Step 6: Create Sketch, Load, and Run Experiments Source Code

Takeaways

7. Just for the Fun of It

Getting Started with VGA-Displayed Arcade Games

How It Works Loading a Game

Step 1: Installing ROMVault Step 2: Running ROMVault Step 3: Programming the FPGA

Source Code and ROM Files

Getting Started with LED Dot Matrix–Displayed Arcade Games

How It Works Design

Step 1: Open Example Design

Experiments Source Code

Takeaways

8. Cha-Ching!

Getting Started with the Bitcoin Miner

How It Works Design Source Code

Takeaways

9. I Hear You!

Getting Started with the SDR Receiver

How It Works Red Pitaya Setup

Loading the SDR

Step 1: Copy Red Pitaya SD Card Image Step 2: Install SDR Applications on PC Step 3: Connect Red Pitaya to the Network Step 4: Run SDR Applications Source Code

Takeaways

A. FPGA Boards B. Papilio AVR Loading

Step 1: Power Up Step 2: Change Circuit Directive Step 3: Load FPGA Bit File Step 4: Change COM Port Step 5: Compile and Upload Sketch

Serial Monitor

Additional Resources

C. Text and Code Editor Index

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