Digital Design Using VHDL · A Systems Approach by Dally, William J. -- Read -- Imperial Library of Trantor

Index

Coverpage Halftitle page Title page Copyright page Contents Preface Acknowledgments Part I Introduction

1 The digital abstraction

1.1 Digital signals 1.2 Digital signals tolerate noise 1.3 Digital signals represent complex data

1.3.1 Representing the day of the year 1.3.2 Representing subtractive colors

1.4 Digital logic functions 1.5 VHDL description of digital circuits and systems 1.6 Digital logic in systems Summary Bibliographic notes Exercises

2 The practice of digital system design

2.1 The design process

2.1.1 Specification 2.1.2 Concept development and feasibility 2.1.3 Partitioning and detailed design 2.1.4 Verification

2.2 Digital systems are built from chips and boards 2.3 Computer-aided design tools 2.4 Moore’s law and digital system evolution Summary Bibliographic notes Exercises

Part II Combinational logic

3 Boolean algebra

3.1 Axioms 3.2 Properties 3.3 Dual functions 3.4 Normal form 3.5 From equations to gates 3.6 Boolean expressions in VHDL Summary Bibliographic notes Exercises

4 CMOS logic circuits

4.1 Switch logic 4.2 Switch model of MOS transistors 4.3 CMOS gate circuits

4.3.1 Basic CMOS gate circuit 4.3.2 Inverters, NANDs, and NORs 4.3.3 Complex gates 4.3.4 Tri-state circuits 4.3.5 Circuits to avoid

Summary Bibliographic notes Exercises

5 Delay and power of CMOS circuits

5.1 Delay of static CMOS gates 5.2 Fan-out and driving large loads 5.3 Fan-in and logical effort 5.4 Delay calculation 5.5 Optimizing delay 5.6 Wire delay 5.7 Power dissipation in CMOS circuits

5.7.1 Dynamic power 5.7.2 Static power 5.7.3 Power scaling

Summary Bibliographic notes Exercises

6 Combinational logic design

6.1 Combinational logic 6.2 Closure 6.3 Truth tables, minterms, and normal form 6.4 Implicants and cubes 6.5 Karnaugh maps 6.6 Covering a function 6.7 From a cover to gates 6.8 Incompletely specified functions 6.9 Product-of-sums implementation 6.10 Hazards Summary Bibliographic notes Exercises

7 VHDL descriptions of combinational logic

7.1 The prime number circuit in VHDL

7.1.1 A VHDL design entity 7.1.2 The case statement 7.1.3 The case? statement 7.1.4 The if statement 7.1.5 Concurrent signal assignment statements 7.1.6 Selected signal assignment statements 7.1.7 Conditional signal assignment statements 7.1.8 Structural description 7.1.9 The decimal prime number function

7.2 A testbench for the prime number circuit 7.3 Example: a seven-segment decoder Summary Bibliographic notes Exercises

8 Combinational building blocks

8.1 Multi-bit notation 8.2 Decoders 8.3 Multiplexers 8.4 Encoders 8.5 Arbiters and priority encoders 8.6 Comparators 8.7 Shifters 8.8 Read-only memories 8.9 Read–write memories 8.10 Programmable logic arrays 8.11 Data sheets 8.12 Intellectual property Summary Bibliographic notes Exercises

9 Combinational examples

9.1 Multiple-of-3 circuit 9.2 Tomorrow circuit 9.3 Priority arbiter 9.4 Tic-tac-toe Summary Exercises

Part III Arithmetic circuits

10 Arithmetic circuits

10.1 Binary numbers 10.2 Binary addition 10.3 Negative numbers and subtraction 10.4 Multiplication 10.5 Division Summary Exercises

11 Fixed- and floating-point numbers

11.1 Representation error: accuracy, precision, and resolution 11.2 Fixed-point numbers

11.2.1 Representation 11.2.2 Operations

11.3 Floating-point numbers

11.3.1 Representation 11.3.2 Denormalized numbers and gradual underflow 11.3.3 Floating-point multiplication 11.3.4 Floating-point addition/subtraction

Summary Bibliographic note Exercises

12 Fast arithmetic circuits

12.1 Carry look-ahead 12.2 Booth recoding 12.3 Wallace trees 12.4 Synthesis notes Summary Bibliographic notes Exercises

13 Arithmetic examples

13.1 Complex multiplication 13.2 Converting between fixed- and floating-point formats

13.2.1 Floating-point format 13.2.2 Fixed- to floating-point conversion 13.2.3 Floating- to fixed-point conversion

13.3 FIR filter Summary Bibliographic note Exercises

Part IV Synchronous sequential logic

14 Sequential logic

14.1 Sequential circuits 14.2 Synchronous sequential circuits 14.3 Traffic-light controller 14.4 State assignment 14.5 Implementation of finite-state machines 14.6 VHDL implementation of finite-state machines Summary Bibliographic notes Exercises

15 Timing constraints

15.1 Propagation and contamination delay 15.2 The D flip-flop 15.3 Setup- and hold-time constraints 15.4 The effect of clock skew 15.5 Timing examples 15.6 Timing and logic synthesis Summary Bibliographic notes Exercises

16 Datapath sequential logic

16.1 Counters

16.1.1 A simpler counter 16.1.2 Up/down/load counter 16.1.3 A timer

16.2 Shift registers

16.2.1 A simple shift register 16.2.2 Left/right/load (LRL) shift register 16.2.3 Universal shifter/counter

16.3 Control and data partitioning

16.3.1 Example: vending machine FSM 16.3.2 Example: combination lock

Summary Exercises

17 Factoring finite-state machines

17.1 A light flasher 17.2 Traffic-light controller Summary Exercises

18 Microcode

18.1 Simple microcoded FSM 18.2 Instruction sequencing 18.3 Multi-way branches 18.4 Multiple instruction types 18.5 Microcode subroutines 18.6 Simple computer Summary Bibliographic notes Exercises

19 Sequential examples

19.1 Divide-by-3 counter 19.2 SOS detector 19.3 Tic-tac-toe game 19.4 Huffman encoder/decoder

19.4.1 Huffman encoder 19.4.2 Huffman decoder

Summary Bibliographic note Exercises

Part V Practical design

20 Verification and test

20.1 Design verification

20.1.1 Verification coverage 20.1.2 Types of tests 20.1.3 Static timing analysis 20.1.4 Formal verification 20.1.5 Bug tracking

20.2 Test

20.2.1 Fault models 20.2.2 Combinational testing 20.2.3 Testing redundant logic 20.2.4 Scan 20.2.5 Built-in self-test (BIST) 20.2.6 Characterization

Summary Bibliographic notes Exercises

Part VI System design

21 System-level design

21.1 System design process 21.2 Specification

21.2.1 Pong 21.2.2 DES cracker 21.2.3 Music player

21.3 Partitioning

21.3.1 Pong 21.3.2 DES cracker 21.3.3 Music synthesizer

Summary Bibliographic notes Exercises

22 Interface and system-level timing

22.1 Interface timing

22.1.1 Always valid timing 22.1.2 Periodically valid signals 22.1.3 Flow control

22.2 Interface partitioning and selection 22.3 Serial and packetized interfaces 22.4 Isochronous timing 22.5 Timing tables

22.5.1 Event flow 22.5.2 Pipelining and anticipatory timing

22.6 Interface and timing examples

22.6.1 Pong 22.6.2 DES cracker 22.6.3 Music player

Summary Exercises

23 Pipelines

23.1 Basic pipelining 23.2 Example pipelines 23.3 Example: pipelining a ripple-carry adder 23.4 Pipeline stalls 23.5 Double buffering 23.6 Load balance 23.7 Variable loads 23.8 Resource sharing Summary Bibliographic notes Exercises

24 Interconnect

24.1 Abstract interconnect 24.2 Buses 24.3 Crossbar switches 24.4 Interconnection networks Summary Bibliographic notes Exercises

25 Memory systems

25.1 Memory primitives

25.1.1 SRAM arrays 25.1.2 DRAM chips

25.2 Bit-slicing and banking memory 25.3 Interleaved memory 25.4 Caches Summary Bibliographic notes Exercises

Part VII Asynchronous logic

26 Asynchronous sequential circuits

26.1 Flow-table analysis 26.2 Flow-table synthesis: the toggle circuit 26.3 Races and state assignment Summary Bibliographic notes Exercises

27 Flip-flops

27.1 Inside a latch 27.2 Inside a flip-flop 27.3 CMOS latches and flip-flops 27.4 Flow-table derivation of the latch 27.5 Flow-table synthesis of a D flip-flop Summary Bibliographic notes Exercises

28 Metastability and synchronization failure

28.1 Synchronization failure 28.2 Metastability 28.3 Probability of entering and leaving an illegal state 28.4 Demonstration of metastability Summary Bibliographic notes Exercises

29 Synchronizer design

29.1 Where are synchronizers used? 29.2 Brute-force synchronizer 29.3 The problem with multi-bit signals 29.4 FIFO synchronizer Summary Bibliographic notes Exercises

Part VIII Appendix: VHDL coding style and syntax guide

Appendix A: VHDL coding style

A.1 Basic principles A.2 All state should be in explicitly declared registers A.3 Define combinational design entities so that they are easy to read A.4 Assign all signals under all conditions A.5 Keep design entities small A.6 Large design entities should be structural A.7 Use descriptive signal names A.8 Use symbolic names for subfields of signals A.9 Define constants A.10 Comments should describe intention and give rationale, not state the obvious A.11 Never forget you are defining hardware A.12 Read and be a critic of VHDL code

Appendix B: VHDL syntax guide

B.1 Comments, identifiers, and keywords B.2 Types

B.2.1 Std_logic B.2.2 Boolean B.2.3 Integer B.2.4 Std_logic_vector B.2.5 Subtypes B.2.6 Enumeration B.2.7 Arrays and records B.2.8 Qualified expressions

B.3 Libraries, packages, and using multiple files B.4 Design entities B.5 Slices, concatenation, aggregates, operators, and expressions B.6 Concurrent statements

B.6.1 Concurrent signal assignment B.6.2 Component instantiation

B.7 Multiple signal drivers and resolution functions B.8 Attributes B.9 Process statements

B.9.1 The process sensitivity list and execution timing B.9.2 Wait and report statements B.9.3 If statements B.9.4 Case and matching case statements B.9.5 Signal and variable assignment statements

B.10 Synthesizable process statements

B.10.1 Type 1: purely combinational B.10.2 Type 2: edge-sensitive B.10.3 Type 3: edge-sensitive with asynchronous reset

References Index of VHDL design entities Subject index

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