Prentice Hall PTR · Verilog HDL · A Guide to Digital Design and Synthesis · 2nd Edition by Palnitkar, Samir -- Read -- Imperial Library of Trantor

Index

Main Page Table of content Copyright About the Author List of Figures List of Tables List of Examples Foreword Preface

Who Should Use This Book How This Book Is Organized Conventions Used in This Book

Acknowledgments Part 1: Basic Verilog Topics

Chapter 1. Overview of Digital Design with Verilog HDL

1.1 Evolution of Computer-Aided Digital Design 1.2 Emergence of HDLs 1.3 Typical Design Flow 1.4 Importance of HDLs 1.5 Popularity of Verilog HDL 1.6 Trends in HDLs

Chapter 2. Hierarchical Modeling Concepts

2.1 Design Methodologies 2.2 4-bit Ripple Carry Counter 2.3 Modules 2.4 Instances 2.5 Components of a Simulation 2.6 Example 2.7 Summary 2.8 Exercises

Chapter 3. Basic Concepts

3.1 Lexical Conventions 3.2 Data Types 3.3 System Tasks and Compiler Directives 3.4 Summary 3.5 Exercises

Chapter 4. Modules and Ports

4.1 Modules 4.2 Ports 4.3 Hierarchical Names 4.4 Summary 4.5 Exercises

Chapter 5. Gate-Level Modeling

5.1 Gate Types 5.2 Gate Delays 5.3 Summary 5.4 Exercises

Chapter 6. Dataflow Modeling

6.1 Continuous Assignments 6.2 Delays 6.3 Expressions, Operators, and Operands 6.4 Operator Types 6.5 Examples 6.6 Summary 6.7 Exercises

Chapter 7. Behavioral Modeling

7.1 Structured Procedures 7.2 Procedural Assignments 7.3 Timing Controls 7.4 Conditional Statements 7.5 Multiway Branching 7.6 Loops 7.7 Sequential and Parallel Blocks 7.8 Generate Blocks 7.9 Examples 7.10 Summary 7.11 Exercises

Chapter 8. Tasks and Functions

8.1 Differences between Tasks and Functions 8.2 Tasks 8.3 Functions 8.4 Summary 8.5 Exercises

Chapter 9. Useful Modeling Techniques

9.1 Procedural Continuous Assignments 9.2 Overriding Parameters 9.3 Conditional Compilation and Execution 9.4 Time Scales 9.5 Useful System Tasks 9.6 Summary 9.7 Exercises

Part 2: Advanced VerilogTopics

Chapter 10. Timing and Delays

10.1 Types of Delay Models 10.2 Path Delay Modeling 10.3 Timing Checks 10.4 Delay Back-Annotation 10.5 Summary 10.6 Exercises

Chapter 11. Switch-Level Modeling

11.1 Switch-Modeling Elements 11.2 Examples 11.3 Summary 11.4 Exercises

Chapter 12. User-Defined Primitives

12.1 UDP basics 12.2 Combinational UDPs 12.3 Sequential UDPs 12.4 UDP Table Shorthand Symbols 12.5 Guidelines for UDP Design 12.6 Summary 12.7 Exercises

Chapter 13. Programming Language Interface

13.1 Uses of PLI 13.2 Linking and Invocation of PLI Tasks 13.3 Internal Data Representation 13.4 PLI Library Routines 13.5 Summary 13.6 Exercises

Chapter 14. Logic Synthesis with Verilog HDL

14.1 What Is Logic Synthesis? 14.2 Impact of Logic Synthesis 14.3 Verilog HDL Synthesis 14.4 Synthesis Design Flow 14.5 Verification of Gate-Level Netlist 14.6 Modeling Tips for Logic Synthesis 14.7 Example of Sequential Circuit Synthesis 14.9 Exercises

Chapter 15. Advanced Verification Techniques

15.1 Traditional Verification Flow 15.2 Assertion Checking 15.3 Formal Verification 15.4 Summary

Part 3: Appendices

Appendix A. Strength Modeling and Advanced Net Definitions

A.1 Strength Levels A.2 Signal Contention A.3 Advanced Net Types

Appendix B. List of PLI Routines

B.1 Conventions B.2 Access Routines B.3 Utility (tf_) Routines

Appendix C. List of Keywords, System Tasks, and Compiler Directives

C.1 Keywords C.2 System Tasks and Functions C.3 Compiler Directives

Appendix D. Formal Syntax Definition

D.1 Source Text D.2 Declarations D.3 Primitive Instances D.4 Module and Generated Instantiation D.5 UDP Declaration and Instantiation D.6 Behavioral Statements D.7 Specify Section D.8 Expressions D.9 General Endnotes

Appendix E. Verilog Tidbits

Origins of Verilog HDL Interpreted, Compiled, Native Compiled Simulators Event-Driven Simulation, Oblivious Simulation Cycle-Based Simulation Fault Simulation General Verilog Web sites Architectural Modeling Tools High-Level Verification Languages Simulation Tools Hardware Acceleration Tools In-Circuit Emulation Tools Coverage Tools Assertion Checking Tools Equivalence Checking Tools Formal Verification Tools

Appendix F. Verilog Examples

F.1 Synthesizable FIFO Model F.2 Behavioral DRAM Model

Bibliography

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